- 您現(xiàn)在的位置：買賣IC網 > PDF目錄385934 > TLV5630EVM (Texas Instruments, Inc.) TLV5630 Evaluation Module(TLC5630評估板) PDF資料下載
參數(shù)資料
| 型號： | TLV5630EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TLV5630 Evaluation Module(TLC5630評估板) |
| 中文描述： | TLV5630評估模塊（TLC5630評估板） |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 395K |
| 代理商： | TLV5630EVM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Processor Controlled Testing
3-6
3.2.4
Serial Clock
When the serial clock is supplied from an external host, jumper W18 must be
in position 2-3. The serial clock can be supplied via the common connector
interface at J11-21 or J6-3. Check the appropriate device data sheet for
maximum serial clock specifications.
3.2.5
Load DAC
The load DAC(/LDAC) pin is designed to simultaneously update all of the DAC
outputs with the current conversion data. This is an asynchronous pin that can
be held low permanently, if simultaneous updates are not required. This pin
is held at a low state by default on the EVM via pulldown resistor R27. This sig-
nal can be controlled through J9-5. DSP users can select to control /LDAC
from either DC_A13 at J10-13 or DC_CNTL0 at J11-64 through jumper W15.
3.2.6
MODE
Jumper W4 controls the signal level on the mode pin of U3 and U4. When
operated in DSP mode, W4 should be closed (MODE = 0). This causes the
DAC outputs to update after the 16
th
falling clock edge.
Opening W4 causes U3 and U4 to operate in microprocessor mode
(MODE = 1). In this condition, frame sync must be asserted high after the 16
th
falling clock edge, or the conversion will be lost.
3.2.7
Power Down
The four-channel device at U5 has a power-down pin that can be accessed
from J9-3. A low level on this pin will send the device into power-down mode.
DSP users can select either DC_CNTRL1 at J11-63 or DC_A12 via W16 as
the source of this control.
相關PDF資料 |
PDF描述 |
|---|---|
| TLV5613(中文) | 2.7V TO 5.5V 12-Bit Parallel DAC With Power Down(具有掉電功能的2.7V至5.5V,12位并行DAC) |
| TLV5614(中文) | 2.7V to 5.5V 12-Bit 3us Quadruple Digital-to-Analog Converters With Power Down(具有掉電功能的2.7V至5.5V,12位,3微秒,四路DAC) |
| TLV5616(中文) | 2.7V TO 5.5V 12-Bit DAC With Serial Power Down(具有掉電功能的2.7V至5.5V,12位串行DAC) |
| TLV5617A(中文) | 2.7V To 5.5V Low Power Dual 10-Bit Digital-To-Analog Converter With Internal Reference And Power Down(低功耗,帶內部基準和掉電的雙10位D/A轉換器) |
| TLV5617AD | RECTEXAS INSTRUMENTSFIER,2 AMP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLV5630IDW | 功能描述:數(shù)模轉換器- DAC 12bit 8Chl DAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5630IDW | 制造商:Texas Instruments 功能描述:IC's |
| TLV5630IDWG4 | 功能描述:數(shù)模轉換器- DAC 2.7V to 5.5V 12-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5630IDWR | 功能描述:數(shù)模轉換器- DAC 2.7V to 5.5V 12-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5630IDWRG4 | 功能描述:數(shù)模轉換器- DAC 2.7V to 5.5V 12-Bit 8-Ch Ser W/Int Ref RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。