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參數(shù)資料
| 型號(hào)： | TLV5624D |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Ultra Fast Recovery Power Rectifier; Repetitive Reverse Voltage Max, Vrrm:100V; Package/Case:DO-220AA; Forward Current:1A; Forward Voltage:0.90V; Peak Surge Current:50A; Reverse Recovery Time:25ns |
| 中文描述： | 2.7 V至5.5 V低功耗的8位數(shù)字至模擬轉(zhuǎn)換器，具有內(nèi)部參考和斷電 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 236K |
| 代理商： | TLV5624D |
TLV5624
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235 – JULY 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
reference pin configured as input (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
RI
CI
Input voltage
0
VDD–1.5
V
Input resistance
10
M
pF
MHz
Input capacitance
5
Reference input bandwidth
REF = 0 2 V
REF = 0.2 Vpp + 1.024 V dc
+ 1 024 V dc
Fast
1.3
Slow
525
kHz
Reference feedthrough
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
–80
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
Ci
High-level digital input current
VI = VDD
VI = 0 V
1
Low-level digital input current
–1
Input capacitance
8
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
See Note 11
CL = 100 pF,
Fast
1
3
μ
s
,
Slow
3.5
7
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code to code
RL = 10 k
See Note 12
CL = 100 pF,
Fast
0.5
1.5
μ
s
,
Slow
1
2
SR
Slew rate
RL = 10 k
See Note 13
CL = 100 pF,
Fast
8
V/
μ
s
,
Slow
1.5
Glitch energy
DIN = 0 to 1,
CS = VDD
fCLK = 100 kHz,
5
nV–S
SNR
Signal-to-noise ratio
53
57
S/(N+D)
Signal-to-noise + distortion
fs = 480 kSPS, fout
RL = 10 k
,
48
47
dB
THD
Total harmonic distortion
CL = 100 pF
,
–50
–48
Spurious free dynamic range
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
50
62
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV5624DGK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN |
| TLV5624ID | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8bit DAC w/Pwr D RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5624IDG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 1.0-3.5us DAC Serial Out RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5624IDGK | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8bit DAC w/Pwr D RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5624IDGKG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 1.0-3.5us DAC Serial Out RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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