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參數(shù)資料
| 型號： | TLV5616I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN |
| 中文描述： | 2.7 V至5.5 V低功耗12位數(shù)字至模擬與電源降壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 310K |
| 代理商： | TLV5616I |
TLV5616C, TLV5616I
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS152B – DECEMBER 1997 – REVISED MARCH 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
CL = 100 pF,
MIN
TYP
MAX
5.5
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
,
See Note 11
Fast
3
μ
s
Slow
9
20
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code to code
RL = 10 k
See Note 12
CL = 100 pF,
Fast
1
μ
s
μ
s
,
Slow
2
SR
Slew rate
RL = 10 k
See Note 13
CL = 100 pF,
Fast
3.6
V/
μ
s
,
Slow
0.9
Glitch energy
Code transition from 0x7FF to 0x800
10
nV–s
S/N
Signal to noise
74
dB
S/(N+D)
Signal to noise + distortion
fs = 400 KSPS
RL = 10 k
,
BW = 20 kHz
fout = 1.1 kHz,
CL = 100 pF,
66
dB
THD
Total harmonic distortion
–68
dB
Spurious free dynamic range
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
70
dB
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–FS)
tsu(FS–CK)
Setup time, CS low before FS
↓
Setup time, FS low before first negative SCLK edge
10
ns
8
ns
tsu(C16–FS)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
10
ns
tsu(C16–CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10
ns
twH
twL
tsu(D)
th(D)
twH(FS)
Pulse duration, SCLK high
25
ns
Pulse duration, SCLK low
25
ns
Setup time, data ready before SCLK falling edge
8
ns
Hold time, data held valid after SCLK falling edge
5
ns
Pulse duration, FS high
20
ns
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| TLV5616IDGK | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12bit DAC w/Pwr D RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5616IDGKG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7-5.5 V Low Power 12-Bit RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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