參數(shù)資料
型號: TLV5608IYE
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 10-BIT DAC, PBGA20
封裝: WAFER CHIP SCALE, 20 PIN
文件頁數(shù): 13/17頁
文件大小: 347K
代理商: TLV5608IYE
TLV5610IYE
TLV5608IYE
SLAS393 OCTOBER 2003
www.ti.com
5
DIGITAL INPUT TIMING REQUIREMENTS
PARAMETER
MIN
TYP
MAX
UNIT
tsu(FS-CK)
Setup time, FS low before first negative SCLK edge
8
ns
tsu(C16-FS)
Setup time, 16th negative edge after FS low on which bit D0 is sampled before rising
edge of FS.
C mode only
10
ns
twL(LDAC)
LDAC duration low
10
ns
twH
SCLK pulse duration high
16
ns
twL
SCLK pulse duration low
16
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
FS duration high
10
ns
twL(FS)
FS duration low
10
ns
ts
Settling time
See AC
specs
相關(guān)PDF資料
PDF描述
TLV5610IDW SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5610IPW SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5610IDWG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5610IPWRG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5610IPWG4 SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PDSO20
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