參數(shù)資料
型號： TLV5604D
廠商： Texas Instruments, Inc.
英文描述： 2.7-V TO 5.5-V 10-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
中文描述： 2.7 V至5.5 V的10位3毫秒翻兩番數(shù)字至模擬與電源降壓轉(zhuǎn)換器
文件頁數(shù)： 7/27頁
文件大小： 359K
代理商： TLV5604D
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
μ
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
(unless otherwise noted) (continued)
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–FS)
tsu(FS–CK)
Setup time, CS low before FS
↓
Setup time, FS low before first negative SCLK edge
10
ns
8
ns
tsu(C16–FS)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
10
ns
tsu(C16–CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10
ns
twH
twL
tsu(D)
th(D)
twH(FS)
Pulse duration, SCLK high
25
ns
Pulse duration, SCLK low
25
ns
Setup time, data ready before SCLK falling edge
8
ns
Hold time, data held valid after SCLK falling edge
5
ns
Pulse duration, FS high
20
ns
PARAMETER MEASUREMENT INFORMATION
tsu(D)
1
2
3
4
5
15
16
D15
D14
D13
D12
D1
D0
tsu(FS-CK)
tsu(CS-FS)
twH(FS)
th(D)
twH
twL
tsu(C16-CS)
tsu(C16-FS)
SCLK
DIN
CS
FS
Figure 1. Timing Diagram
相關PDF資料
PDF描述
TLV5604PW 2.7-V TO 5.5-V 10-BIT 3-mS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5606D 2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5606DGK 2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
TLV5613DW 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TLV5613PW 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
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TLV5604ID 制造商:Texas Instruments 功能描述:Digital-Analog Converter IC Interface Ty
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