參數(shù)資料
型號(hào)： TLV5604CDG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝： GREEN, PLASTIC, SOIC-16
文件頁(yè)數(shù)： 5/31頁(yè)
文件大?。?/td> 572K
代理商： TLV5604CDG4
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5604 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
FSX
DX
CLKX
TLV5604
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5604
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5604
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5604. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
SCLKmax +
1
t
wH(min) )
t
wL(min)
+ 20 MHz
The maximum update rate is:
f
UPDATEmax +
1
16
t
wH(min) )
t
wL(min)
+ 1.25 MHz
Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the
TLV5604 has to be considered also.
data format
The 16-bit data word for the TLV5604 consists of two parts:
D Control bits
(D15 . . . D12)
D New DAC value
(D11 ...D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A1
A0
PWR
SPD
New DAC value (10 bits)
X
X: don’t care
SPD: Speed control bit.
1
→ fast mode
0
→ slow mode
PWR: Power control bit.
1
→ power down
0
→ normal operation
相關(guān)PDF資料
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TLV5604IPWRG4 SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
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