參數(shù)資料
型號: TLV5592D
廠商: Texas Instruments, Inc.
英文描述: 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEX PAGER CHIPSET
中文描述: 2位模擬數(shù)字轉(zhuǎn)換器對于Flex尋呼機(jī)芯片組
文件頁數(shù): 6/15頁
文件大?。?/td> 208K
代理商: TLV5592D
TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEX PAGER CHIPSET
SLAS145A – JUNE1996 – REVISED DECEMBER 1997
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Value A
Value B
Based on Value A
Based on Value B
CLK
TRACKINH
(external)
TRACKINH
(internal)
Peak/Valley
Counter Value
EXTS0, EXTS1
Outputs
(See Note A)
NOTE A: Internally the device recognizes input conditions on the falling edge of the clock only.
Figure 1. Timing Diagram
CLK
CON1
CON2
TRACKINH
NOTES: A. Internally the device recognizes input conditions on the falling edge of the clock only.
B. On the next falling edge of the clock with the input conditions shown, the TLV5592 tracks signal in fast track mode (peak DAC
counter counts down by 8 and up by 4) in time A.
C. On the next falling edge of the clock with the input conditions shown, the TLV5592 tracks signal in slow track mode (peak DAC
counter counts up by 2 and down by 1 every 40 clock cycles) in time B.
D. On the next falling edge of the clock with the input conditions shown, the TLV5592 holds previous peak and valley levels in time
C. For the 2-bit output, when TRACKINH = 1, EXTS0 and EXTS1 outputs respond in real time to the condition of SIG and DC
OFFSET as long as the CLK signal is present.
(See Note B)
(See Note C)
(See Note D)
Time A
Time B
Time C
See Note A
Figure 2. Track and Lock Timing
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