參數(shù)資料
型號(hào): TLV320ALC23
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: Evaluation Platform for the TLV320ALC23 Stereo Audio CODEC and TLV230DAC23 Stereo DAC
中文描述: 評(píng)估平臺(tái)為TLV320ALC23 DAC的立體聲音頻編解碼器和立體聲TLV230DAC23
文件頁(yè)數(shù): 24/46頁(yè)
文件大?。?/td> 452K
代理商: TLV320ALC23
SLAS428 AUGUST 2004
www.ti.com
24
SPI DIGITAL INTERFACE
All ’DAC26 control registers are programmed through a standard SPI bus. The SPI allows full-duplex, synchronous, serial
communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the
synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize
transmissions.
A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the slave SPIDIN
(MOSI) pin under the control of the master serial clock. As the byte shifts in on the SPIDIN pin, a byte shifts out on the
SPIDOUT (MISO) pin to the master shift register.
The idle state of the serial clock for the ’DAC26 is low, which corresponds to a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0). The ’DAC26 interface is designed so that with a clock phase bit setting of 1
(typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its
SPIDOUT pin on the first serial clock edge. The SS pin can remain low between transmissions; however, the ’DAC26 only
interprets command words which are transmitted after the falling edge of SS.
Hardware Reset
The device requires a low-to-high pulse on RESET after power up for correct operation. A hardware reset pulse initializes
all the internal registers, counters, and logic.
Hardware Power Down
By default the PWD pin is configured as a hardware power-down (active low) signal. The device powers down all the internal
circuitry to save power. All the register contents are maintained. Some counters maintain their value.
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