參數(shù)資料
型號: TLV320AIC11C
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: General-Purpose Low-Voltage 1.1V to 3.6V/0 16-bit 22-KSPS DSP CODEC
中文描述: 通用低電壓1.1V至3.6V的/ 0 16位22 kSPS的DSP的解碼器
文件頁數(shù): 12/55頁
文件大小: 263K
代理商: TLV320AIC11C
1–6
1.6
Definitions and Terminology
Data transfer interval
The time during which data is transferred from DOUT to DIN. The interval is 16 shift clocks
and the data transfer is initiated by the falling edge of the FS signal.
This refers to the input signal and all of the converted representations through the ADC
channel, and the signal through the DAC channel to the analog output. This is in contrast
with the purely-digital software control data.
Primary communication refers to the digital data-transfer interval. Since the device is syn-
chronous, the signal data words from the ADC channel and to the DAC channel occur si-
multaneously.
Secondary communication refers to the digital control and configuration data-transfer in-
terval into DIN, and the register read-data cycle from DOUT. The data transfer occurs when
requested by hardware or software.
Serial peripheral interface
Frame/pulse sync refers only to the falling edge of the signal FS that initiates the data-
transfer interval. The primary FS starts the primary communication, and the secondary FS
starts the secondary communication.
Frame/Pulse sync and sampling period is the time between falling edges of successive
primary FS signals and it is always equal to 256xSCLK if the number of cascading devices
is less than 5, or 512 xSCLK if the number of cascading devices is greater than 4.
The sampling frequency
ADC channel refers to all signal-processing circuits between the analog input and the
digital conversion result at DOUT.
DAC channel refers to all signal-processing circuits between the digital data word applied
to DIN and the differential output analog signal available at OUTP and OUTM.
A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.
Bit position in the primary data word (xx is the bit number).
Bit position in the secondary data word (xx is the bit number).
The alpha character drepresents valid programmed or default data in the control-register
format (see Section 3.2, Secondary Serial Communication) when discussing other data bit
portions of the register.
Programmable gain amplifier
Finite-duration impulse response
Direct configuration serial interface for host control
Signal data
Primary
communication
Secondary
communication
SPI
Frame/pulse sync
Frame/pulse sync and
sampling period
f
s
ADC channel
DAC channel
Host
Dxx
DSxx
d
PGA
FIR
DCSI
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