參數(shù)資料
型號(hào): TLV320AIC1107PWRG4
廠商: Texas Instruments
文件頁(yè)數(shù): 5/20頁(yè)
文件大?。?/td> 0K
描述: IC PCM CODEC PROG MICAMP 20TSSOP
標(biāo)準(zhǔn)包裝: 2,000
類型: PCM
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 13 b
ADC / DAC 數(shù)量: 1 / 1
三角積分調(diào)變:
電壓 - 電源,模擬: 2.7 V ~ 3.3 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
配用: 296-18387-ND - DEVELOPMENT PLATFORM DSP-CODEC
TLV320AIC1107
SLAS360 DECEMBER 2001
13
www.ti.com
PRINCIPLES OF OPERATION
receive volume control
In linear mode, RXVOL [2:0] PCM data bits are used for volume control according to Table 3. Volume control
bits must be sent on PCMI for each 13-bit receive word. In companded mode, volume control is fixed at 0 dB.
Table 3. Volume Control Bit Definition in Linear Mode
RXVOL [2:0]
GAIN SETTING
000
3 dB
001
0 dB
010
3 dB
011
6 dB
100
9 dB
101
12 dB
110
15 dB
111
18 dB
support section
The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive
internal counters, filters, and converters.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 kHz determines the sampling rate. The PCMSYN signal must be derived from the
master clock. The divide ratio must be set to 256 for the device to work properly.
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相關(guān)代理商/技術(shù)參數(shù)
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