參數(shù)資料
型號(hào)： TLV2731IDBV
廠商： Texas Instruments, Inc.
英文描述： Advanced LinCMOSE RAIL-TO-RAIL LOW-POWER SINGLE OPERATIONAL AMPLIFIERS
中文描述： 高級(jí)LinCMOSE軌至軌低功率運(yùn)算放大器
文件頁(yè)數(shù)： 26/28頁(yè)
文件大小： 631K
代理商： TLV2731IDBV
TLV2731, TLV2731Y
Advanced LinCMOS
RAIL-TO-RAIL
LOW-POWER SINGLE OPERATIONAL AMPLIFIERS
SLOS198 – AUGUST 1997
26
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts
, the model generation software used
with Microsim PSpice
. The Boyle macromodel (see Note 6) and subcircuit in Figure 57 are generated using
the TLV2731 typical electrical and operating characteristics at T
A
= 25
°
C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits,SC-9, 353 (1974).
OUT
+
–
+
–
53
+
–
+
–
+
–
+
–
+
–
+
–
+
–
.SUBCKT TLV2731 1 2 3 4 5
C1
C2
DC
DE
DLP
DLN
DP
EGND
FB
+ VLN 0 90.83E3 –10E3 10E3 10E3 –10E3
GA
6
GCM
0
ISS
3
HLIM
90
J1
11
J2
12
R2
6
11
6
5
54
90
92
4
99
7
12
7
53
5
91
90
3
0
99
13.51E–12
50.00E–12
DX
DX
DX
DX
DX
POLY (2) (3,0) (4,0) 0 .5 .5
POLY (5) VB VC VE VLP
0
6
10
0
2
1
9
11
10
DC
VLIM 1K
10 JX
10 JX
100.0E3
12 314.2E–6
99 242.35E–9
87.00E–6
RD1
RD2
R01
R02
RP
RSS
VAD
VB
VC
VE
VLIM
VLP
VLN
.MODEL DX D (IS=800.0E–18)
.MODEL JX PJF (IS=500.0E–15 BETA=2.939E–3
+ VTO=–.065)
.ENDS
60
60
8
7
3
10
60
9
3
54
7
91
0
11
12
5
99
4
99
4
0
53
4
8
0
92
3.183E3
3.183E3
25
25
6.553E3
2.500E6
–.5
DC 0
DC .795
DC .795
DC 0
DC 12.4
DC 17.4
VDD+
RP
IN –
2
IN+
1
VDD–
VAD
RD1
11
J1
J2
10
RSS
ISS
3
12
RD2
60
VE
54
DE
DP
VC
DC
4
C1
R2
6
9
EGND
VB
FB
C2
GCM
GA
VLIM
8
5
RO1
RO2
HLIM
90
DLP
91
DLN
92
VLN
VLP
99
7
Figure 56. Boyle Macromodel and Subcircuit
PSpice and Partsare trademark of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI,
directly or indirectly, are not warranted by TI as fully representing all
of the specification and operating characteristics of the
semiconductor product to which the model relates.
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