參數(shù)資料
型號: TLV2543CDBLE
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封裝: PLASTIC, SSOP-20
文件頁數(shù): 9/28頁
文件大?。?/td> 553K
代理商: TLV2543CDBLE
TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B7
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
DATA INPUT
CS
EOC
Initialize
Hi-Z
(see Note A)
B3
B2
B1
B0
t(conv)
Figure 12. Timing for 8-Clock Transfer Using CS With MSB First
Access Cycle B
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B7
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
12
3
4
5
6
7
8
1
I/O CLOCK
DATA OUT
DATA INPUT
CS
EOC
Initialize
(see Note A)
B3
B2
B1
B0
t(conv)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Figure 13. Timing for 8-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control
input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
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