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參數(shù)資料
| 型號(hào)： | TLV1549MJG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| 中文描述： | 10位模擬數(shù)字轉(zhuǎn)換器與串行控制 |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | TLV1549MJG |
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TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C – JANUARY 1993 – REVISED MARCH 1995
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz
PARAMETER
TEST CONDITIONS
MIN
MAX
±
1
±
1
±
1
±
1
UNIT
Linearity error (see Note 6)
LSB
Zero error (see Note 7)
See Note 2
LSB
Full-scale error (see Note 7)
See Note 2
LSB
Total unadjusted error (see Note 8)
LSB
μ
s
tconv
Conversion time
See Figures 6–11
21
tc
Total cycle time (access, sample, and conversion)
See Figures 6–11
and Note 9
21
+10 I/O
CLOCK
periods
μ
s
tv
td(I/O-DATA)
tPZH, tPZL
tPHZ, tPLZ
tr(bus)
tf(bus)
td(I/O-CS)
NOTES:
Valid time, DATA OUT remains valid after I/O CLOCK
↓
Delay time, I/O CLOCK
↓
to DATA OUT valid
Enable time, CS
↓
to DATA OUT (MSB driven)
Disable time, CS
↑
to DATA OUT (high impedance)
Rise time, data bus
See Figure 5
10
ns
See Figure 5
240
ns
μ
s
ns
See Figure 3
1.3
See Figure 3
180
See Figure 5
300
ns
Fall time, data bus
Delay time, 10th I/O CLOCK
↓
to CS
↓
to abort conversion (see Note10)
2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ – Vref–); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero, and full-scale errors.
9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the tenth I/O CLOCK (see Figure 5).
10. Any transitions of CS are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of
the internal clock (1.425
μ
s) after the transition.
See Figure 5
300
ns
μ
s
9
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