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參數(shù)資料
| 型號： | TLIU04C1 |
| 英文描述： | TLIU04C1 Quad T1/E1 Line Interface |
| 中文描述： | TLIU04C1四T1/E1線路接口 |
| 文件頁數(shù)： | 69/100頁 |
| 文件大小： | 1321K |
| 代理商： | TLIU04C1 |
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Advance Data Sheet, Rev. 2
April 1999
TLIU04C1 Quad T1/E1 Line Interface
69
Lucent Technologies Inc.
Direct Logic Control Mode
(continued)
Data Recovery
The receive line interface unit (RLIU) format is bipolar
alternate mark inversion (AMI). The data rate tolerance
is ±130 ppm (DS1) or ±80 ppm (CEPT). The receiver
first restores the incoming data and detects analog loss
of signal. Subsequent processing is optional and
depends on the programmable device configuration
established with the use of the direct logic control pins.
The RLIU utilizes an equalizer to operate on line length
with up to 15 dB of loss at 772 kHz (DS1) or 13 dB loss
at 1.024 MHz (CEPT). The signal is then peak-
detected and sliced to produce digital representations
of the data.
Clock and data recovery, digital loss of signal, jitter
attenuation, and data decoding are performed. The
receive digital output format is non-return-to-zero
(NRZ) with selectable dual-rail or single-rail system
interface.
The clock is recovered by a digital phase-locked loop
that uses XCLK as a reference to lock to the data rate
component. Because the internal reference clock is a
multiple of the received data rate, the RCLK output will
always be a valid DS1/CEPT clock that eliminates
false-lock conditions. During periods with no receive
input signal, the free-run frequency of RCLK is defined
to be either XCLK/16 or XCLK, depending on the state
of CLKS. RCLK is always active with a duty-cycle cen-
tered at 50%, deviating by no more than ±5%. Valid
data is recovered within the first few bit periods after
the application of XCLK. The delay of the data through
the receive circuitry is approximately 1 to 14 bit peri-
ods, depending on the CODE configurations. Additional
delay is introduced if the jitter attenuator is selected for
operation in the receive path (see the LIU Delay Values
section, page 89).
Jitter Accommodation and Jitter Transfer
Without the Jitter Attenuator
The RLIU is designed to accommodate large amounts
of input jitter. The RLIU’s jitter performance exceeds
the requirements shown in the RLIU Specifications
tables (Table 43 and Table 44). Typical receiver perfor-
mance without the jitter attenuator in the path is shown
in Figure 27 through Figure 30. Jitter transfer is inde-
pendent of input ones density on the line interface.
Receiver Configuration Modes
Clock/Data Recovery Mode (CDR)
The clock/data recovery function in the receive path
can be bypassed by setting the FLLOOP RLOOP and
DLLOOP pins for all channels low. Any other combina-
tion of the twelve loopback pins results in the clock and
data recovery function being enabled and providing a
recovered clock (RCLK) with retimed data (RPD/
RDATA, RND). If all twelve of the loopback pins are
asserted, the clock and data recovery function is dis-
abled, and the RZ data from the slicers is provided over
RPD and RND to the system. In this mode, down-
stream functions selected by the JAR, ACM, and
LOSSD pins are ignored.
Zero Substitution Decoding (CODE)
When single-rail operation is selected with DUAL = 0,
the B8ZS/HDB3 decoding can be selected. CODE[1—
4] pulled high selects the B8ZS/HDB3 decoding opera-
tion for each individual channel.
Note:
Encoding and decoding are not independent.
Selecting B8ZS/HDB3 decoding in the receiver
selects B8ZS/HDB3 encoding in the transmitter.
When decoding is selected for a given channel,
decoded receive data and code violations appear on
the RDATA and BPV pins, respectively. If coding is not
selected, receive data and any bipolar violations (such
as two consecutive ones of the same polarity) appear
on the RDATA and BPV pins, respectively.
Alternate Logic Mode (ALM)
The alternate logic mode (ALM) control pin selects the
receive and transmit data polarity (i.e., active-high vs.
active-low). If ALM = 0, the receiver circuitry (and trans-
mit input) assumes the data to be active-low polarity. If
ALM = 1, the receiver circuitry (and transmit input)
assumes the data to be active-high polarity. The ALM
control is used in conjunction with the ACM control to
determine the receive data retiming mode.
Alternate Clock Mode (ACM)
The alternate clock mode (ACM) control pin selects the
positive or negative clock edge of the receive clock
(RCLK) for receive data retiming. The ACM control is
used in conjunction with the ALM control to determine
the receive data retiming modes. If ACM = 1, the
receive data is retimed on the positive edge of the
receive clock. If ACM = 0, the receive data is retimed
on the negative edge of the receive clock. Note that this
control does not affect the timing relationship for the
transmitter inputs. See Figure 38 on page 97.
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