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參數(shù)資料
| 型號： | TLE6240GP |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Smart 16-fold Low-Side Switch |
| 中文描述： | 智能16倍的低邊開關(guān) |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 814K |
| 代理商： | TLE6240GP |
Data Sheet TLE 6240 GP
V3.1
Page
26.Aug 2002
5
Electrical Characteristics
Parameter and Conditions
V
S
= 4.5 to 5.5 V ; T
j
= - 40 °C to + 150 °C; Reset = H
(unless otherwise specified)
Symbol
Values
min
Unit
typ
max
1. Power Supply, Reset
Supply Voltage
4
Supply Current
Supply Current in Standby Mode (RESET = L)
Minimum Reset Duration
(After a reset all parallel inputs are ORed with the SPI
data bits)
V
S
I
S
I
S(stdy)
t
Reset,min
4.5
--
--
10
--
5
10
--
5.5
10
50
--
V
mA
μA
μs
2. Power Outputs
ON Resistance V
S
= 5 V
Channel 1 ... 8
ON Resistance V
S
= 5 V
Channel 10, 11, 14, 15
ON Resistance V
S
= 5 V
Channel 9, 12, 13, 16
Output Clamping Voltage
Output OFF
Current Limit
T
J
= 25°C
T
J
= 150°C
T
J
= 25°C
T
J
= 150°C
T
J
= 25°C
T
J
= 150°C
Channel 1-8
Channel 9-16
Channel 1...8
Channel 9...16
V
Reset
= L
R
DS(ON)
--
--
--
--
--
--
45
45
1
1.7
0.35
0.60
0.30
0.50
50
52,5
1.3
2.2
0.40
0.70
0.35
0.60
60
60
R
DS(ON)
R
DS(ON)
V
DS(AZ)
V
I
D(lim)
1
3
1.5
4.5
2
6
A
Output Leakage Current
I
D(lkg)
t
ON
t
OFF
--
--
--
--
6
6
10
12
12
μA
μs
μs
Turn-On Time
Turn-Off Time
I
D
= 0.5 A, resistive load
I
D
= 0.5 A, resistive load
3. Digital Inputs
Input Low Voltage
Input High Voltage
Input Voltage Hysteresis
Input Pull Down/Up Current (IN1...4, IN9...12) V
IN
= 5 V
PRG, Reset Pull Up Current
Input Pull Down Current (SI, SCLK)
Input Pull Up Current (
CS
)
V
INL
V
INH
V
INHys
I
IN(1..4,9...12)
I
IN(PRG,Res)
I
IN(SI,SCLK)
I
IN(CS)
- 0.3
2.0
50
20
20
10
10
--
--
100
50
50
20
20
1.0
--
200
100
100
50
50
V
V
mV
μA
μA
μA
μA
4. Digital Outputs (SO,
FAULT
)
SO High State Output Voltage
SO Low State Output Voltage
Output Tri-state Leakage Current
FAULT Output Low Voltage
I
SOH
= 2 mA
I
SOL
= 2.5 mA
CS
= H, 0
≤
V
SO
≤
V
S
I
FAULT
= 1.6 mA
V
SOH
V
SOL
I
SOlkg
V
FAULTL
V
S
- 0.4 --
--
-10
--
--
0.4
10
0.4
V
V
--
0
--
μA
V
4
For V
S
< 4.5V the power stages are switched according the input signals and data bits or are definitely switched
off. This undervoltage reset gets active at V
S
= 3V (typ. value) and is guaranteed by design.
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