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參數(shù)資料
| 型號： | TLE6232 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Smart Six Channel Low-Side Switch |
| 中文描述： | 智能六通道低端開關(guān) |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 349K |
| 代理商： | TLE6232 |
Data Sheet TLE 6232 GP
V1.2
Page
08.Oct. 2003
9
SPI Signal Description
CS
- Chip Select. The system microcontroller selects the TLE 6232 GP by means of the
CS
pin. Whenever the pin is in a logic low state, data can be transferred from the μC and vice
versa.
CS
High to Low transition:
- diagnostic status information is transferred from the
power
outputs into the shift register.
- serial input data can be clocked in from then on
- SO changes from high impedance state to logic high or low
state corresponding to the SO bits
CS
Low to High transition:
-
transfer of SI bits from shift register into output buffers
- reset of diagnosis register
To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of
CS
. When
CS
is in a logic high state, any signals at the SCLK and
SI pins are ignored and SO is forced into a high impedance state.
SCLK
- Serial Clock. The system clock pin clocks the internal shift register of the TLE
6232 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever
chip select
CS
makes any transition. The number of clock pulses will be counted during a
chip select cycle. The received data will only be accepted, if exactly 16 clock pulses were
counted during
CS
is active.
SI
- Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-
mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of two bytes - a "control byte” followed by a "data byte". The control
byte contains the information as to whether the data byte will be accepted or ignored (see di-
agnostics section). The data byte contains the input information for the six channels. A logic
high level at this pin (within the data byte) will switch on the power switch, provided that the
corresponding parallel input is also switched on (AND-operation for channel 1 to 6).
SO
- Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant
bit first. SO is in a high impedance state until the
CS
pin goes to a logic low state. New diag-
nostic data will appear at the SO pin following the rising edge of SCLK.
RESET
- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip.
In case of inactive chip select signal (High) or bit 7 and bit 6 of the instruction byte differing
from1“ and 0“ the data output SO remains into tri-state.
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| TLE6232GP | Smart Six Channel Low-Side Switch |
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| TLE6244X | 18 Channel Smart Lowside Switch |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLE6232GP | 功能描述:電源開關(guān) IC - 配電 SMART 6 CHANNEL LW-SIDE SWITCH RoHS:否 制造商:Exar 輸出端數(shù)量:1 開啟電阻（最大值）:85 mOhms 開啟時間（最大值）:400 us 關(guān)閉時間（最大值）:20 us 工作電源電壓:3.2 V to 6.5 V 電源電流（最大值）: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOT-23-5 |
| TLE6232GP_09 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Smart Six Channel Low-Side Switch |
| TLE6232GPAUMA2 | 制造商:Infineon Technologies AG 功能描述:Power Switch Lo Side 1.5A 36-Pin DSO EP 制造商:Infineon Technologies AG 功能描述:ENGINECONTROL_IC - Tape and Reel 制造商:Infineon Technologies AG 功能描述:IC SW SMART 6-CH LOWSIDE PDSO36 |
| TLE6232GPNT | 制造商:Infineon Technologies AG 功能描述:Power Switch Lo Side 1.5A 36-Pin DSO |
| TLE6232GPT | 制造商:Infineon Technologies AG 功能描述:Power Switch Lo Side 1.5A 36-Pin DSO T/R |
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