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TLE 6210
TLE 6211
Block Description and Electrical Characteristics
V1.2 Data Sheet
25
2002-08
Figure 8
Missing watchdog signals cause EN low
Figure 9
Timing diagram - any watchdog signal missing causes a High signal
at the output "=15" (Counter reset). This signal sets back the logic
1
0
1
0
1
0
15*t
CLK
+ Delay
= 15*t
CLK
+ 3* t
CLK
WD1
WD2
EN
Delay (3* t
CLK
)
t < 15 *t
CLK
Delay (3* t
CLK
)
15*t
CLK
wd-controls-en
AD 03/02
10ms
1
0
1
0
1
0
10ms
WD1
WD2
EN
WD Signal not detected
(15+3) * t
CLK
1
0
Counter Reset
16* t
CLK
wd-missing
AD 03/02