參數(shù)資料
型號: TLC546I
廠商: Texas Instruments, Inc.
英文描述: 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS
中文描述: 8位模擬數(shù)字轉(zhuǎn)換器與串行控制和19輸入端
文件頁數(shù): 5/13頁
文件大小: 184K
代理商: TLC546I
TLC545C, TLC545I, TLC546C, TLC546I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 19 INPUTS
SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
TLC545
NOM
TLC546
NOM
UNIT
MIN
MAX
MIN
MAX
Supply voltage, VCC
Positive reference voltage, Vref+ (see Note 2)
Negative reference voltage, Vref– (see Note 3)
Differential reference voltage, Vref+ – Vref– (see Note 3)
Analog input voltage (see Note 3)
4.75
5
5.5
4.75
5
5.5
V
0
VCC
VCC +0.1
0
VCC
VCC +0.1
V
–0.1
0
VCC
–0.1
0
VCC
V
0
VCC
VCC +0.2
0
VCC
VCC +0.2
V
0
VCC
0
VCC
V
High-level control input voltage, VIH
Low-level control input voltage, VIL
Setup time, address bits at data input before I/O CLOCK
,
tsu(A)
Address hold time, th
2
2
V
0.8
0.8
V
200
400
ns
0
0
ns
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 2)
3
3
System
clock
cycles
I/O CLOCK frequency, fclock(I/O)
SYSTEM CLOCK frequency, fclock(SYS)
0
2.048
0
1.1
MHz
fclock(I/O)
4
fclock(I/O)
2.1
MHz
Pulse duration, CS high during conversion, twH(CS)
36
36
System
clock
cycles
Pulse duration, SYSTEM CLOCK high, twH(SYS)
Pulse duration, SYSTEM CLOCK low, twL(SYS)
Pulse duration, I/O CLOCK high, twH(I/O)
Pulse duration, I/O CLOCK low, twL(I/O)
110
210
ns
100
190
ns
200
404
ns
200
404
ns
System
fclock(SYS)
1048 kHz
fclock(SYS) > 1048 kHz
fclock(I/O)
525 kHz
fclock(I/O) > 525 kHz
TLC545C, TLC546C
30
30
ns
Clock transition time
(see Note 4)
20
20
I/O
100
100
ns
40
40
Operating free air temperature TA
Operating free-air temperature, TA
0
70
0
70
TLC545I, TLC546I
–40
85
–40
85
°
C
NOTES:
2. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling
edge or rising edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address
data until the minimum chip select setup time has elapsed.
3. Analog input voltages greater than that applied to REF+ convert as all “1”s (11111111), while input voltages less than that applied
to REF– convert as all “0”s (00000000). As the differential reference voltage decreases below 4.75 V, the total unadjusted error tends
to increase.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2
μ
s for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
相關PDF資料
PDF描述
TLC545C 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS
TLC545I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 19 INPUTS
TLC548C 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
TLC548I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
TLC549C 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
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