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參數(shù)資料
| 型號： | TLC34076-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(110MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（110MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 47/56頁 |
| 文件大?。?/td> | 419K |
| 代理商： | TLC34076-110 |
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B-1
Appendix B
PC Board Layout Considerations
PC Board Considerations
A four-layer PC board should be used with the TLC34076: one layer each for 5-V power and GND and two
layers for signals. The layout should be optimized for the lowest-possible noise on the TLC34076 power and
ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups
of V
DD
and GND pins should be minimized so as to reduce inductive ringing. The terminal assignments for
the TLC34076 P<0:31> inputs were selected for minimum interconnect lengths between these inputs and
the VRAM pixel data outputs. The TLC34076 should be located as close to the output connectors as
possible to minimize noise pickup and reflections due to impedance mismatching.
Ground Plane
A single ground plane is recommended for both the TLC34076 and the rest of the logic. Separate digital and
analog ground planes are not needed.
Power Plane
Split power planes are recommended for the TLC34076 and the rest of the logic. The TLC34076 and its
associated analog circuitry should have their own power plane (referred to as A
VCC
in Figure B–1). The two
power planes should be connected at a single point through a ferrite bead as shown in Figures B–1, B–2,
and B–3. This bead should be located within three inches of the TLC34076.
Supply Decoupling
Bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation,
to reduce the lead inductance.
For the best performance, a 0.1-
μ
F ceramic capacitor in parallel with a 0.01-
μ
F chip capacitor should be
used to decouple each of the three groups of power pins to GND. These capacitors should be placed as
close as possible to the device as shown in Figure B–2.
If a switching power supply is used, the designer should pay close attention to reducing power supply noise
and should consider using a three-terminal voltage regulator for supplying power to A
VCC
.
COMP and V
REF
Terminals
A 100-
resistor (optional) and 0.1-
μ
F ceramic capacitor (approximate values) should be connected in
series between the device’s COMP and V
DD
terminals in order to avoid noise and color-smearing problems.
Also, whether an internal or external voltage reference is used, a 0.1-
μ
F capacitor should be connected
between the device’s V
REF
and GND terminals to further stabilize the video image. These resistor and
capacitor values may vary depending on the board layout; experimentation may be required in order to
determine optimum values.
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