參數(shù)資料
型號： TLC34075A-85
廠商： Texas Instruments, Inc.
英文描述： Color-Palette(85MHz,視頻接口調(diào)色器)
中文描述： 顏色調(diào)色板（85MHz，視頻接口調(diào)色器）
文件頁數(shù)： 17/53頁
文件大?。?/td> 394K
代理商： TLC34075A-85
FUNCTION
SCLK
BITS
2. . . 0
divide DOTCLK by
BITS
5. . .3
VCLK
divide
DOTCLK
by
2-4
Table 2–4. Output Clock Selection Register Format
BITS
3
0
1
0
1
0
1
X
X
X
X
X
X
X
X
5
0
0
0
0
1
1
1
X
X
X
X
X
X
X
4
0
0
1
1
0
0
1
X
X
X
X
X
X
X
2
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
X
X
X
X
X
X
X
0
1
0
1
0
1
X
VCLK frequency = DOTCLK frequency
VCLK frequency = DOTCLK frequency/2
VCLK frequency = DOTCLK frequency/4
VCLK frequency = DOTCLK frequency/8
VCLK frequency = DOTCLK frequency/16
VCLK frequency = DOTCLK frequency/32
VCLK output held at logic high level (default condition)§
SCLK frequency = DOTCLK frequency
SCLK frequency = DOTCLK frequency/2
SCLK frequency = DOTCLK frequency/4
SCLK frequency = DOTCLK frequency/8
SCLK frequency = DOTCLK frequency/16
SCLK frequency = DOTCLK frequency/32
SCLK output held at logic level low (default condition)§
Register bits 6 and 7 are don’t carebits.
When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are
stabilized and running.
§These lines indicate the power-up conditions required to support the VGA pass-through mode.
Table 2–5. VCLK/SCLK Divide Ratio Selection
(Output Clock Selection Register Value in Hex)
000
001
010
011
100
101
1
2
4
8
16
32
000
001
010
011
100
101
1
2
4
8
00
08
10
18
20
28
01
09
11
19
21
29
02
0A
12
1A
22
2A
03
0B
13
1B
23
2B
04
0C
14
1C
24
2C
05
0D
15
1D
25
2D
16
32
Output clock selection register bits
2.3.1
SCLK
The TLC34075A latches data on the rising edge of the LOAD signal (LOAD is the same as SCLK but is not
disabled while the BLANK signal is active). Therefore, SCLK must be set as a function of the pixel bus width
and the number of bit planes. The SCLK frequency can be selected to be the same as the dot clock
frequency or 1/2, 1/4, 1/8, 1/16, or 1/32 of the dot clock frequency. If SCLK is not used, the output is switched
off and held low to protect against VRAM lock-up due to invalid SCLK frequencies. SCLK is also held low
during the BLANK signal active period. The control timing has been designed to bring the first pixel data
ready from the VRAM when BLANK is disabled and ready for the display. When split shift register transfer
operation is used, SCLK is taken care of by working with SSRT input (see Section 2.9).
Refer to Figure 2–2 for the following timing explanation.
相關(guān)PDF資料
PDF描述
TLC3544IDWR 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
TLC3544IPWR 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
TLC3544IPWRG4 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
TLC3544CDWRG4 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
TLC3544IDWRG4 5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC34076 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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TLC34076-85FN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
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TLC34077135FN 制造商:TI 功能描述:*
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