參數(shù)資料
型號: TLC1543QN
廠商: Texas Instruments, Inc.
英文描述: OSC 5V SMT 7X5 CMOS
中文描述: 10位模擬數(shù)字轉(zhuǎn)換器與串行控制和11個(gè)模擬輸入
文件頁數(shù): 10/27頁
文件大小: 424K
代理商: TLC1543QN
TLC1542C, TLC1542I, TLC1542M TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052E – MARCH 1992 – OCTOBER 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
±
0.5
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
UNIT
LSB
TLC1542C, I, or Q
EL
Linearity error (see Note 6)
TLC1543C, I, or Q
LSB
TLC1542M
LSB
TLC1542C, I, or Q
See Note 2
LSB
EZS
Zero-scale error (see Note 7)
TLC1543C, I, or Q
See Note 2
LSB
TLC1542M
See Note 2
LSB
TLC1542C, I, or Q
See Note 2
LSB
EFS
Full-scale error (see Note 7)
TLC1543C, I, or Q
See Note 2
LSB
TLC1542M
See Note 2
LSB
TLC1542C, I, or Q
LSB
Total unadjusted error (see Note 8)
TLC1543C, I, or Q
LSB
TLC1542M
LSB
ADDRESS = 1011
512
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1100
0
ADDRESS = 1101
1023
tconv
Conversion time
See timing diagrams
21
μ
s
tc
Total cycle time (access, sample, and conversion)
See timing diagrams
and Note 10
21
+10 I/O
CLOCK
periods
μ
s
tacq
Channel acquisition time (sample)
See timing diagrams
and Note 10
6
I/O
CLOCK
periods
tv
td(I/O-DATA)
td(I/O-EOC)
td(EOC-DATA)
All typical values are at TA = 25
°
C.
NOTES:
2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ – Vref–); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
Valid time, DATA OUT remains valid after I/O CLOCK
Delay time, I/O CLOCK
to DATA OUT valid
Delay time, tenth I/O CLOCK
to EOC
Delay time, EOC
to DATA OUT (MSB)
See Figure 6
10
ns
See Figure 6
240
ns
See Figure 7
70
240
ns
See Figure 8
100
ns
相關(guān)PDF資料
PDF描述
TLC1542MFK 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
TLC1542MJ 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
TLC1542C 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
TLC1542I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
TLC1542M 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
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