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參數(shù)資料
| 型號： | TLC0820AINE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 345K |
| 代理商： | TLC0820AINE4 |
TLC0820AC, TLC0820AI
Advanced LinCMOS
HIGH-SPEED 8-BIT ANALOG-TO-DIGITAL
CONVERTERS USING MODIFIED FLASH TECHNIQUES
SLAS064A – SEPTEMBER 1986 – REVISED JUNE 1994
2–3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ANLG IN
1
I
Analog input
CS
13
I
Chip select. CS must be low in order for RD or WR to be recognized by the ADC.
D0
2
O
Digital, 3-state output data, bit 1 (LSB)
D1
3
O
Digital, 3-state output data, bit 2
D2
4
O
Digital, 3-state output data, bit 3
D3
5
O
Digital, 3-state output data, bit 4
D4
14
O
Digital, 3-state output data, bit 5
D5
15
O
Digital, 3-state output data, bit 6
D6
16
O
Digital, 3-state output data, bit 7
D7
17
O
Digital, 3-state output data, bit 8 (MSB)
GND
10
Ground
INT
9
O
Interrupt. In the write-read mode, the interrupt output (INT) going low indicates that the internal count-down delay
time, td(int), is complete and the data result is in the output latch. The delay time td(int) is typically 800 ns starting
after the rising edge of WR (see operating characteristics and Figure 3). If RD goes low prior to the end of td(int),
INT goes low at the end of td(RIL) and the conversion results are available sooner (see Figure 2). INT is reset by
the rising edge of either RD or CS.
MODE
7
I
Mode select. MODE is internally tied to GND through a 50-
A current source, which acts like a pulldown resistor.
When MODE is low, the read mode is selected. When MODE is high, the write-read mode is selected.
NC
19
No internal connection
OFLW
18
O
Overflow. Normally OFLW is a logical high. However, if the analog input is higher than Vref+, OFLW will be low at
the end of conversion. It can be used to cascade two or more devices to improve resolution (9 or 10 bits).
RD
8
I
Read. In the write-read mode with CS low, the 3-state data outputs D0 through D7 are activated when RD goes
low. RD can also be used to increase the conversion speed by reading data prior to the end of the internal
count-down delay time. As a result, the data transferred to the output latch is latched after the falling edge of RD.
In the read mode with CS low, the conversion starts with RD going low. RD also enables the 3-state data outputs
on completion of the conversion. RDY going into the high-impedance state and INT going low indicate completion
of the conversion.
REF –
11
I
Reference voltage. REF – is placed on the bottom of the resistor ladder.
REF +
12
I
Reference voltage. REF + is placed on the top of the resistor ladder.
VCC
20
Power supply voltage
WR/RDY
6
I/O
Write ready. In the write-read mode with CS low, the conversion is started on the falling edge of the WR input signal.
The result of the conversion is strobed into the output latch after the internal count-down delay time, td(int), provided
that the RD input does not go low prior to this time. The delay time td(int) is approximately 800 ns. In the read mode,
RDY (an open-drain output) goes low after the falling edge of CS and goes into the high-impedance state when
the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system.
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| TLC0820ACDBR | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
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| TLC0820ACDWR | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
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