- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383949 > TL16C552AHV (Texas Instruments, Inc.) DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO PDF資料下載
參數(shù)資料
| 型號： | TL16C552AHV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO |
| 中文描述： | 雙異步通信元帶有FIFO |
| 文件頁數(shù)： | 35/39頁 |
| 文件大小： | 545K |
| 代理商： | TL16C552AHV |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁
TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
35
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
programming
The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written to in any order, the IER should be written to last because it controls
the interrupt enables. Once the serial channel is programmed and operational, these registers can be updated
any time the ACE serial channel is not transmitting or receiving data.
receiver
Serial asynchronous data is input into SIN. The ACE continually searches for a high-to-low transition
from the idle state. When the transition is detected, a counter is reset and counts the 16
×
clock to 7 1/2, which
is the center of the start bit. The start bit is valid if SIN is still low. Verifying the start bits prevents the receiver
from assembling a false data character due to a low-going noise spike on the SIN input.
The LCR determines the number of data bits in a character (LCR0 and LCR1). When parity is used, LCR3 and
the polarity of parity LCR4 is needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indicator in LSR0 is set. The CPU reads the receiver
buffer register, which clears LSR0. If the character is not read prior to a new character transfer from the RSR
to the RBR, the overrun error status indicator is set in LSR1. If there is a parity error, the parity error is set in
LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.
If the data into SIN is a symmetrical square wave, the center of the data cells occurs within
±
3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16
×
clock cycle
prior to being detected.
scratchpad register
The scratch register is an 8-bit read/write register that has no effect on either channel in the ACE. It is intended
to be used by the programmer to hold data temporarily.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TL16C552AMFN | DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO |
| TL16C554AI | ASYNCHRONOUS-COMMUNICATIONS ELEMENT |
| TL16C554I | ASYNCHRONOUS COMMUNICATIONS ELEMENT |
| TL2575-15I | 1-A SIMPLE STEP-DOWN SWITCHING VOLTAGE REGULATORS |
| TL2575-33I | 1-A SIMPLE STEP-DOWN SWITCHING VOLTAGE REGULATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TL16C552AIFN | 功能描述:UART 接口集成電路 Dual UART w/16-Byte FIFOs & Para Port RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C552AIFNG4 | 功能描述:UART 接口集成電路 Dual UART w/ 16-Byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C552AM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO |
| TL16C552AMFN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO |
| TL16C552AMHV | 制造商:Texas Instruments 功能描述:UART 2-CH 16Byte FIFO 5V 68-Pin CFPAK Tube 制造商:Rochester Electronics LLC 功能描述:DUAL 550 UART WITH CENTRONIX PORT - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。