參數(shù)資料
型號： TL16C550CI
廠商： Texas Instruments, Inc.
英文描述： Asynchronous Communications Element With Autoflow Control(帶自動數(shù)據(jù)流控制異步通信器件)
中文描述： 異步通信元件與Autoflow技術控制（帶自動數(shù)據(jù)流控制異步通信器件）
文件頁數(shù)： 23/39頁
文件大?。?/td> 556K
代理商： TL16C550CI
TL16C550C, TL16C550CI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177F
–
MARCH 1994
–
REVISED MARCH 2001
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB
A2
A1
A0
REGISTER
0
L
L
L
Receiver buffer (read), transmitter holding register (write)
0
L
L
H
Interrupt enable register
X
L
H
L
Interrupt identification register (read only)
X
L
H
L
FIFO control register (write)
X
L
H
H
Line control register
X
H
L
L
Modem control register
X
H
L
H
Line status register
X
H
H
L
Modem status register
X
H
H
H
Scratch register
1
L
L
L
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal
is controlled by writing to this bit location (see Table 4).
Table 2. ACE Reset Functions
REGISTER/SIGNAL
RESET CONTROL
RESET STATE
Interrupt enable register
Master reset
All bits cleared (0
–
3 forced and 4
–
7 permanent)
Interrupt identification register
Master reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4
–
5 are
permanently cleared
FIFO control register
Master reset
All bits cleared
Line control register
Master reset
All bits cleared
Modem control register
Master reset
All bits cleared (6
–
7 permanent)
Line status register
Master reset
Bits 5 and 6 are set; all other bits are cleared
Modem status register
Master reset
Bits 0
–
3 are cleared; bits 4
–
7 are input signals
SOUT
Master reset
High
INTRPT (receiver error flag)
Read LSR/MR
Low
INTRPT (received data available)
Read RBR/MR
Low
INTRPT (transmitter holding register empty)
Read IR/write THR/MR
Low
INTRPT (modem status changes)
Read MSR/MR
Low
OUT2
Master reset
High
RTS
Master reset
High
DTR
Master reset
High
OUT1
Master reset
High
Scratch register
Master reset
No effect
Divisor latch (LSB and MSB) registers
Master reset
No effect
Receiver buffer register
Master reset
No effect
Transmitter holding register
Master reset
No effect
RCVR FIFO
MR/FCR1
–
FCR0/
FCR0
MR/FCR2
–
FCR0/
FCR0
All bits cleared
XMIT FIFO
All bits cleared
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相關代理商/技術參數(shù)
參數(shù)描述
TL16C550CIFN 功能描述:UART 接口集成電路 Sngl UART w/16-Byte FIFOs & Aut Flw Ctrl RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIFNG4 功能描述:UART 接口集成電路 Sgl UART w/ 16-Byte FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIFNR 功能描述:UART 接口集成電路 Sgl UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIFNRG4 功能描述:UART 接口集成電路 Sgl UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C550CIN 制造商:TI 制造商全稱:Texas Instruments 功能描述:ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL
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