參數(shù)資料
型號(hào)： TL16C550B(中文)
廠商： Texas Instruments, Inc.
英文描述： Asynchronous Communications Elememt(帶16字節(jié)FIFO的單路異步通信組件，可直接代替NS的NS16550A)
中文描述： 異步通信Elememt（帶16字節(jié)的FIFO的單路異步通信組件，可直接代替納秒的NS16550A）
文件頁(yè)數(shù)： 16/23頁(yè)
文件大?。?/td> 569K
代理商： TL16C550B(中文)
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4. 2 FIFO′÷￡¨FCR￡
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l
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REGISTER ADDRESS
0 DLAB =0
0DLAB =0
1 DLAB =0
2
2
3
4
5
6
7
0 DLAB =1
1DLAB =1
Bit
No.
Receiver
Buffer
Register
(Read
Only)
RBR
Transmitter
Holding
Register
(Write
Only)
THR
Interrupt
Enable
Register
Interrupt
Ident.
Register
(Read
Only)
IIR
FIFO
Control
Register
(Write
Only)
FCR
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Latch
(MSB)
IER
LCR
MCR
LSR
MSR
SCR
DLL
DLM
0
Data Bit 0
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
0 if
interrupt
Pending
FIFO
Enable
Word
Length
Select
Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
(
CTS)
Bit 0
Bit 0
Bit 8
1
Data Bit 1
Data Bit 1
Interrupt
ID
Bit (1)
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(
DSR)
Bit 1
Bit 1
Bit 9
2
Data Bit 2
Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit (2)
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1
Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
3
Data Bit 3
Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit (2)
(see
Note 4)
DMA
Mode
Select
Parity
Enable
(PEN)
OUT2
Framing
Error
(FE)
Delta
Data
Carrier
Detect
(
DCD)
Bit 3
Bit 3
Bit 11
4
Data Bit 4
Data Bit 4
0
0
Reserved
Even
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4
Bit 4
Bit 12
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick
Parity
0
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
6
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(see
Note 4)
Receiver
Trigger
(LSB)
Break
Control
0
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Bit 6
Bit 6
Bit 14
7
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(see
Note 4)
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
(DLAB)
0
Error in
RCVR
FIFO
(see
Note 4)
Data
Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
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