參數(shù)資料
型號: TIBPAL16R8-25CJ
廠商: Texas Instruments, Inc.
英文描述: LOW-POWER HIGH-PERFORMANCE IMPACT E PAL CIRCUITS
中文描述: 低功耗高性能的位置PAL制式電路的影響
文件頁數(shù): 15/19頁
文件大?。?/td> 311K
代理商: TIBPAL16R8-25CJ
TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
LOW-POWER HIGH-PERFORMANCE
IMPACT
PAL
CIRCUITS
SRPS059 – FEBRUARY 1984 – REVISED APRIL 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tdis
tdis
tsu
S1
From Output
Under Test
Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR 3-STATE OUTPUTS
th
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
3.5 V
0.3 V
3.5 V
VOL
+
0.3 V
VOL
VOH
VOH – 0.3 V
0 V
ten
ten
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
R1
3.5 V
0.3 V
7 V
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR
1 MHz, tr = tf
2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.
When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open.
E. Equivalent loads may be used for testing.
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
Figure 3. Load Circuit and Voltage Waveforms
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