參數資料
型號: THS8135PHPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48
封裝: GREEN, PLASTIC, HTQFP-48
文件頁數: 22/25頁
文件大?。?/td> 522K
代理商: THS8135PHPG4
THS8135
TRIPLE 10BIT, 240 MSPS VIDEO DAC WITH TRILEVEL SYNC AND VIDEO
(ITUR.BT601)COMPLIANT FULL SCALE RANGE
SLAS343A MAY 2001 REVISED JUNE 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
generic DAC mode versus video DAC mode (continued)
Because of the eliminated dc bias, the DAC output compliance for full-range video input can be higher in generic
DAC mode: up to 1.286 Vpp at nominal double 75-
termination load. This is high enough for the D/A conversion
of composite video (NTSC/PAL/SECAM), where the signal fed to the device contains the complete digital
composite waveform, including sync and color-burst.
Selection between generic DAC versus video DAC mode is controlled through a combination of SYNC and
SYNC_T settings. Since in video DAC mode, SYNC_T only determines the sync polarity, this signal has don’t
care status when no sync insertion takes place i.e., when SYNC is high. The THS8135 uses the logic level on
the SYNC_T input when SYNC is high to enter generic DAC mode: SYNC_T and SYNC are high
→ generic
DAC mode. Therefore, the user must make sure to keep SYNC_T low outside the sync insertion period (when
SYNC is high) to prevent entering generic DAC mode, when he intends to use the device in video DAC mode.
Table 1 shows how to select between video DAC and generic DAC mode.
Table 1. Video vs Generic Mode Selection
SYNC
BLANK
SYNC_T
OPERATION MODE AND DAC OUTPUT
1
Generic DAC mode. Blanking override inactive.
1
0
1
Generic DAC mode. Blanking override active. Blanking level position is according to the codes of Table 5,
however no dc bias is present on the Y, R, G, and B outputs
1
0
Video DAC mode. Blanking override inactive
1
0
Video DAC mode. Blanking override active. Blanking level position is according to the codes of Table 5, with dc
bias present on the Y, R, G, and B outputs as shown in Figure 1 and Figure 3.
0
X
0
Video DAC mode. Negative sync inserted
0
X
1
Video DAC mode. Positive sync inserted
device configuration using M1 and M2 in video DAC mode
In the video DAC mode, the configuration signals M1 and M2 are both sampled on the second rising edge of
the CLK input signal after a L
→ H or H → L transition on SYNC. Depending on the polarity of this last transition
on SYNC, M1 and M2 are interpreted differently by the THS8135, as shown in Table 2.
NOTE:
In the THS8133, only M2 is a sampled signal while M1 is continuously interpreted. By doing so here,
the additional input control signal BLNK_INT is generated. See the backward compatibility with the
THS8133 section.
Table 2. Interpretation of M1 in Video DAC Mode
If last event on
SYNC is:
Then M1 is interpreted on
the second CLK rising edge
following this event as:
DESCRIPTION
H
→ L
BLNK_INT
Sets operation with full or video (ITUR.BT601) input code range i.e., the full-scale
range is reached from either the 01023 10-bit input code range or the input code range of
Table 6, see also Table 5 for blanking level positions.
L
→H
M1_INT
Sets device operation mode. See Table 4 and Table 5.
Table 3. Interpretation of M2 in VIdeo DAC Mode
If last event on
SYNC is:
Then M2 is interpreted on
the second CLK rising edge
following this event as:
DESCRIPTION
H
→L
INS3_INT
Sets sync Insertion mode: SYNC low enables sync generation on one (INS3_INT=L) or all
three (INS3_INT=H) DAC outputs. SYNC_T determines the sync polarity.
L
→H
M2_INT
Sets device operation mode. See Table 4 and Table 5.
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