參數(shù)資料
型號(hào)： THS8134TQFP
廠商： Texas Instruments, Inc.
英文描述： TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
中文描述： 三路8位，80 MSPS的視頻D /與Tri轉(zhuǎn)爐電平同步發(fā)電
文件頁(yè)數(shù)： 12/24頁(yè)
文件大?。?/td> 346K
代理商： THS8134TQFP
THS8134, THS8134A, THS8134B
TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS205D – MAY 1999 – REVISED MARCH 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions with f
CLK
= 80 MSPS and use
of internal reference voltage V
ref
, with R
(FS)
= R
(FSnom)
(unless otherwise noted) (continued)
digital inputs – dc characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
IIH
IIL
IIL(CLK)
IIH(CLK)
CI
ts
tH
High-level input current
1
Low-level input current
AVDD = DVDD = 5 V
Digital inputs and CLK at 0 V for IIL;
Digital inputs and CLK at 5 V for IIH
Digital in uts and CLK at 5 V for IIH
–1
Low-level input current, CLK
1
μ
A
High-level input current, CLK
–1
Input capacitance
TA = 25
°
C
7
pF
Data and control inputs setup time
3
ns
Data and control inputs hold time
0
ns
Di it l
Digital process d l
component of pixel(see Figures 3–5)
com onent of ixel (see Figures 3–5)
f
fi t
i t
d
l
RGB and YPbPr 4:4:4
YPbPr 4:2:2 2
×
8 bit
YPbPr 4:2:2 1
×
8 bit
7
CLK
periods
td(D)
( )
8
9
This parameter is assured by design and not production tested. The digital process delay is defined as the number of CLK cycles required for
the first registered color component of a pixel, starting from the time of registering it on the input bus, to propagate through all processing and
appear at the DAC output drivers. The remaining delay through the IC is the analog delay td(A) of the analog output drivers.
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