參數(shù)資料
型號(hào): THS8134CPHP
廠(chǎng)商: TEXAS INSTRUMENTS INC
元件分類(lèi): DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 0.005 us SETTLING TIME, 8-BIT DAC, PQFP48
封裝: PLASTIC, HTQFP-48
文件頁(yè)數(shù): 25/27頁(yè)
文件大?。?/td> 553K
代理商: THS8134CPHP
THS8134, THS8134A, THS8134B
TRIPLE 8BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRILEVEL SYNC GENERATION
SLVS205D MAY 1999 REVISED MARCH 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
programming example (continued)
T0
T1
T2
T3
T4
T5
T6
T7
T8
RPr(0)
RPr(1)
RPr(2)
RPr(3)
RPr(4)
RPr(5)
RPr(6)
RPr(7)
RPr(8)
GY(0)
GY(1)
GY(2)
GY(3)
GY(4)
GY(5)
GY(6)
GY(7)
GY(8)
BPb(0)
BPb(1)
BPb(2)
BPb(3)
BPb(4)
BPb(5)
BPb(6)
BPb(7)
BPb(8)
CLK
RPr[70]
GY[70]
BPb[70]
ARPr, AGY,
ABPb output
corresponding to RPr(0),
GY(0), BPb(0)
data path latency = 7 CLK cycles
RPr(0), GY(0), BPb(0)
registered
Figure 3. Input Format and Latency YPbPr 4:4:4 and GBR 4:4:4 Modes
First registered sample on RPr[70] after L-
>H
on BLANK is interpreted as Pb[70]
T0
T1
T2
T3
T4
T5
T6
T7
T8
Pb(0)
Pr(0)
Pb(2)
Pr(2)
Pb(4)
Pr(4)
Pb(6)
Pr(6)
Pb(8)
RPr[70]
ARPr, AGY,
ABPb output
corresponding to Pr(0),
Y(0), Pb(0)
data path latency = 8 CLK cycles
Pb(0), Y(0)
registered
T9
Pr(8)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
Y(5)
Y(6)
Y(7)
Y(8)
GY[70]
Y(9)
BPb[70]
BLANK
Pr(0), Y(1)
registered
Figure 4. Input Format and Latency YPbPr 4:2:2 2
×8 bit Mode
相關(guān)PDF資料
PDF描述
THS8134ACPHP PARALLEL, 8 BITS INPUT LOADING, 0.005 us SETTLING TIME, 8-BIT DAC, PQFP48
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