參數(shù)資料
型號(hào): THS8134BTQFP
廠商: Texas Instruments, Inc.
英文描述: TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER WITH TRI-LEVEL SYNC GENERATION
中文描述: 三路8位,80 MSPS的視頻D /與Tri轉(zhuǎn)爐電平同步發(fā)電
文件頁數(shù): 13/24頁
文件大?。?/td> 346K
代理商: THS8134BTQFP
THS8134, THS8134A, THS8134B
TRIPLE 8-BIT, 80 MSPS VIDEO D/A CONVERTER
WITH TRI-LEVEL SYNC GENERATION
SLVS205D – MAY 1999 – REVISED MARCH 2000
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions with f
CLK
= 80 MSPS and use
of internal reference voltage V
ref
, with R
(FS)
= R
(FSnom)
(unless otherwise noted) (continued)
analog (DAC) outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC resolution
8
8
bits
INL
Integral nonlinearity
Static, best fit
±
0.2
±
0.2
±
1.2
±
1
LSB
DNL
Differential nonlinearity
Static
LSB
PSRR
Power supply ripple rej
output (full scale)
f = 100 kHz (see Note 4)
37
dB
f = 1 MHz (see Note 4)
43
XTALK
Crosstalk between channels
f up to 30 MHz, (see Note 5)
–55
dB
VO(ref)
ro(VREF)
Voltage reference output
1.30
1.35
1.40
V
VREF output resistance
7K
11K
15K
W
G(DAC)
DAC gain factor
See
Table 4
Imbalance between DACs, (KIMBAL)
Imbalance between positive and negative sync,
(KIMBAL(SYNC))
See Note 6
±
5%
See Note 6
±
2%
VO(DAC)
DAC output compliance voltage (sync+video)
RL = 37.5
, See Note 7
RL = 75
, See Note 7
1
1.2
V
2
2.4
Internal reference
AGY
24
26.67
28
GBR sync-on-green and YPbPr sy
on-all
ABPb and ARPr
17.3
18.67
19.7
mA
y
External reference
AGY
24.9
26.67
27.2
I( S)
I(FS)
ABPb and ARPr
17.5
18.67
19.3
Internal reference
AGY
24
26.67
28
GBR sync on all
GBR sync-on-all
ABPb and ARPr
24
26.67
28
mA
External reference
AGY
24.9
26.67
27.2
ABPb and ARPr
24.9
26.67
27.2
ro
CO
tr(DAC)
tf(DAC)
DAC output resistance
See Note 10
57
92
k
DAC output capacitance (pin capacitance)
8
pF
DAC output current rise time
10% to 90% of full scale
2
ns
DAC output current fall time
10% to 90% of full scale
2
ns
td(A)
Analog output delay
Measured from CLK=VIH(min) to 50% of full-scale
transition, See Note 8
9
ns
tS
Analog output settling time
Measured from 50% of full scale transition on output
to output settling, within 2%, See Note 9
5
9
ns
SNR
Signal -to-noise ratio
1 MHz, –1 dBFS digital sine input, measured from
0 MHz to 8.8 MHz
53
dB
SFDR
Spurious-free dynamic range
1 MHz, –1 dBFS digital sine input, measured from
0 MHz to 8.8 MHz
62
dB
BW(1 dB)
NOTES:
Bandwidth
4. PSRR is measured with a 0.1
μ
F capacitor between the COMP and AVDD terminal; with a 0.1
μ
F capacitor connected between the VREF terminal and
AVSS. The ripple amplitude is within the range 100 mVp-p to 500 mVp-p with the DAC output set to full scale and a double-terminated 75
(=37.5
)
load. PSRR is defined as 20
×
log(ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.
5.
Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limits from characterization only.
6.
The imbalance between DACs applies to all possible pairs of the three DACs. KIMBAL is assured over full temperature range. In parts labeled
THS8134CPHP, KIMBAL(SYNC) is assured at 25
°
C. In parts labeled THS8134ACPHP, KIMBAL(SYNC) is assured over the full temperature range.
7.
Nominal values at R(FS) = R(FSnom) : Maximum values at R(FS) = R(FSnom)
÷
1.2. Maximum limits from characterization only.
8.
This value excludes the digital process delay, td(D). Limit from characterization only.
9.
Maximum limit from characterization only
10.
Limit from characterization only
11.
This bandwidth relates to the output amplitude variation in excess of the droop from the sinx/x sampled system. Since the output is a sample-and-hold
signal, a sin(
π
×
Fin
÷
Fclk)
÷
(
π
×
Fin
÷
Fclk) roll-off is observed, which accounts e.g. at Fin = 40 MHz and Fclk = 80 MSPS for –3.92 dB signal drop (sync
droop). The total DAC output variation (device droop) consists of this and an additional amount (excess droop) caused by the output impedance of the
device, as shown in Table 5.
See Note 11
40
MHz
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