Level
Shift
Internal
Circuitry
+V
S
800kW
Input
Pin
www.ti.com
SBOS449A – SEPTEMBER 2008 – REVISED JANUARY 2011
INPUT MODE OF OPERATION: DC
V/V] = 0.51 V. This calculation is true for up to the
maximum recommended 5-V power supply that
The
THS7375
allows
for
both
ac-coupled
and
allows approximately a [(4.9 V – 0.32 V) / 5.6 V/V] =
dc-coupled inputs. Many DACs or video encoders can
0.818 V input range while avoiding clipping on the
be dc-connected to the THS7375. One of the
output.
drawbacks to dc coupling, however, is when 0 V is
applied to the input. Although the input of the
The input impedance of the THS7375 in this mode of
THS7375 allows for a 0-V input signal with no issues,
operation is dictated by the internal 800-k
pull-down
the output swing of a traditional amplifier cannot yield
resistor, as shown in
Figure 49. Note that the internal
a 0-V signal, resulting in possible clipping. This
voltage shift does not appear at the input pin, but only
condition is true for any single-supply amplifier as a
the output pin.
result of output transistor limitations. Both CMOS and
bipolar transistors cannot go to 0 V while sinking
current. This characterization of a transistor is also
the same reason why the highest output voltage is
always less than the power-supply voltage when
sourcing current.
This output clipping can reduce the sync amplitudes
(both horizontal and vertical sync) on the video
signal. A problem occurs if the receiver of this video
signal uses an AGC loop to account for losses in the
transmission line. Some video AGC circuits derive
gain from the horizontal sync amplitude. If clipping
occurs on the sync amplitude, then the AGC circuit
can increase the gain too much—resulting in too
Figure 49. Equivalent DC Input Mode Circuit
much luma and/or chroma amplitude gain correction.
This overcorrection may result in a picture with an
overly bright display with too much color saturation.
INPUT MODE OF OPERATION: AC SYNC-TIP
Other AGC circuits use the chroma burst amplitude
CLAMP
for amplitude control, and a reduction in the sync
Some video DACs or encoders are not referenced to
signals does not alter the proper gain setting.
ground but rather to the positive power supply. The
However, it is good engineering design practice to
resulting video signals are generally at too high of a
ensure that saturation/clipping does not take place.
voltage for a dc-coupled video buffer to function
Transistors always take a finite amount of time to
properly. To account for this scenario, the THS7375
come out of saturation. This saturation could possibly
incorporates a sync-tip clamp (STC) circuit. This
result in timing delays or other aberrations on the
function requires a capacitor (nominally 0.1 mF) to be
signals.
in series with the input. Note that while the term
To
eliminate
saturation/clipping
problems,
the
sync-tip clamp is used throughout this document, it
THS7375 has a 320-mV output level shift feature.
should be noted that the THS7375 would probably be
This feature takes the input voltage and adds an
better termed to be a dc restoration circuit based on
internal shift to the signal. The THS7375 rail-to-rail
how this function is performed. This circuit is an
output stage can create this output level while
active clamp circuit and not a passive diode clamp
connected to a typical video load. This feature
function.
ensures that no saturation/clipping of the sync signals
The input to the THS7375 has an internal control loop
occur. This shift is constant, regardless of the input
that sets the lowest input applied voltage to clamp at
signal. For example, if a 0.4-V input is applied, the
ground (0 V). By setting the reference at 0 V, the
output is at (0.4 V × 5.6 V/V) + 0.32 V = 2.56 V.
THS7375 allows a dc-coupled input to also function.
Because the internal gain is fixed at 5.6 V/V (+14.95
Therefore,
the
STC
is
considered
transparent
dB), the gain dictates what the allowable linear input
because it does not operate unless the input signal
voltage range can be without clipping concerns. For
goes below ground. The signal then goes through the
example, if the power supply is set to 3.3 V, the
same level shifter, resulting in an output voltage low
maximum output is approximately 3.15 V while driving
level of 320 mV. If the input signal tries to go below 0
a significant amount of current. Thus, to avoid
V, the internal control loop of the THS7375 sources
clipping, the allowable input is [(3.2 V – 0.32 V) / 5.6
up to 3 mA of current to increase the input voltage
level on the THS7375 input side of the coupling
capacitor. As soon as the voltage goes above the 0-V
level, the loop stops sourcing current and becomes
very high impedance.
Copyright 2008–2011, Texas Instruments Incorporated
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