參數(shù)資料
型號(hào)： THS7364IPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： 6 CHANNEL, VIDEO AMPLIFIER, PDSO20
封裝： GREEN, PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 24/47頁(yè)
文件大?。?/td> 1134K
代理商： THS7364IPWR
Level
Shift
Internal
Circuitry
+V
S
800kW
Input
Pin
Input
0.1 mF
g
m
+V
S
STCLPF
SBOS530 – AUGUST 2010
www.ti.com
INPUT MODE OF OPERATION: AC SYNC TIP
CLAMP
Some video DACs or encoders are not referenced to
ground but rather to the positive power supply. The
resulting video signals are generally at too great a
voltage for a dc-coupled video buffer to function
properly. To account for this scenario, the THS7364
incorporates a sync-tip clamp circuit. This function
requires a capacitor (nominally 0.1 mF) to be in series
with the input. Although the term sync-tip-clamp is
used throughout this document, it should be noted
that the THS7364 would probably be better termed as
Figure 79. Equivalent AC Sync-Tip-Clamp Input
a dc restoration circuit based on how this function is
Circuit
performed. This circuit is an active clamp circuit and
not a passive diode clamp function.
While this feature may not fully eliminate overshoot
The input to the THS7364 has an internal control loop
issues on the input signal, in cases of extreme
that sets the lowest input applied voltage to clamp at
overshoot and/or ringing, the STC system should help
ground (0 V). By setting the reference at 0 V, the
minimize improper clamping levels. As an additional
THS7364 allows a dc-coupled input to also function.
method to help minimize this issue, an external
Therefore, the sync-tip-clamp (STC) is considered
capacitor (for example, 10 pF to 47 pF) to ground in
transparent because it does not operate unless the
parallel with the external termination resistors can
input signal goes below ground. The signal then goes
help filter overshoot problems.
through the same 150-mV level shifter, resulting in an
output voltage low level of 300 mV. If the input signal
It should be noted that this STC system is dynamic
tries to go below 0 V, the THS7364 internal control
and does not rely upon timing in any way. It only
loop sources up to 6 mA of current to increase the
depends on the voltage that appears at the input pin
input voltage level on the THS7364 input side of the
at any given point in time. The STC filtering helps
coupling capacitor. As soon as the voltage goes
minimize
level
shift
problems
associated
with
above the 0-V level, the loop stops sourcing current
switching noises or very short spikes on the signal
and becomes very high impedance.
line. This architecture helps ensure a very robust
STC system.
One of the concerns about the sync-tip-clamp level is
how the clamp reacts to a sync edge that has
When the ac STC operation is used, there must also
overshoot—common in VCR signals, noise, DAC
be some finite amount of discharge bias current. As
overshoot, or reflections found in poor printed circuit
previously described, if the input signal goes below
board (PCB) layouts. Ideally, the STC should not
the 0-V clamp level, the internal loop of the THS7364
react to the overshoot voltage of the input signal.
sources current to increase the voltage appearing at
Otherwise, this response could result in clipping on
the input pin. As the difference between the signal
the rest of the video signal because it may raise the
level and the 0-V reference level increases, the
bias voltage too much.
amount
of
source
current
increases
proportionally—supplying up to 6 mA of current.
To help minimize this input signal overshoot problem,
Thus, the time to re-establish the proper STC voltage
the control loop in the THS7364 has an internal
can be very fast. If the difference is very small, then
low-pass filter, as shown in Figure 79. This filter
the source current is also very small to account for
reduces the response time of the STC circuit. This
minor voltage droop.
delay is a function of how far the voltage is below
ground, but in general it is approximately a 400-ns
However, what happens if the input signal goes
delay for the SD channel filters and approximately a
above the 0-V input level? The problem is the video
150-ns delay for the FHD filters. The effect of this
signal is always above this level and must not be
filter is to slow down the response of the control loop
altered in any way. Thus, if the sync level of the input
so as not to clamp on the input overshoot voltage but
signal is above this 0-V level, then the internal
rather the flat portion of the sync signal.
discharge (sink) current reduces the ac-coupled bias
signal to the proper 0-V level.
As a result of this delay, sync may have an apparent
voltage shift. The amount of shift depends on the
amount of droop in the signal as dictated by the input
capacitor and the STC current flow. Because sync is
used primarily for timing purposes with syncing
occurring on the edge of the sync signal, this shift is
transparent in most systems.
30
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): THS7364
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