參數(shù)資料
型號： THS5651ADW
廠商： Texas Instruments, Inc.
英文描述： 10-BIT, 125 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 10位，125 MSPS的，CommsDACE數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 5/30頁
文件大?。?/td> 737K
代理商： THS5651ADW
THS5651A
10-BIT, 125 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS260 – FEBRUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, AV
DD
= 5 V,
DV
DD
= 5 V, IOUT
FS
= 20 mA, differential transformer coupled output, 50
doubly terminated load
(unless otherwise noted)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog output
fCLK
Maximum output update rate
DVDD = 4.5 V to 5.5 V
DVDD = 3 V to 3.6 V
100
125
MSPS
70
100
ts(DAC)
tpd
GE
Output settling time to 0.1%
35
ns
Output propagation delay
Glitch energy
Output rise time 10% to 90%
Output fall time 90% to 10%
1
ns
Worst case LSB transition (code 511 – code 512)
5
pV–s
tr(IOUT)
tf(IOUT)
1
ns
1
ns
Output noise
IOUTFS = 20 mA
IOUTFS = 2 mA
15
10
pA/
√
HZ
AC linearity§
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25
°
C
fCLK = 50 MSPS, fOUT = 1 MHz, TA = –40
°
C to 85
°
C
fCLK = 50 MSPS, fOUT = 2 MHz, TA = 25
°
C
fCLK = 100 MSPS, fOUT = 2 MHz, TA = 25
°
C
fCLK = 25 MSPS, fOUT = 1 MHz, TA = 25
°
C
fCLK = 50 MSPS, fOUT= 1 MHz, TA = –40
°
C to 85
°
C
fCLK = 50 MSPS, fOUT = 1 MHz, TA = 25
°
C
fCLK = 50 MSPS, fOUT = 2.51 MHz, TA = 25
°
C
fCLK = 50 MSPS, fOUT = 5.02 MHz, TA = 25
°
C
fCLK = 50 MSPS, fOUT = 20.2 MHz, TA = 25
°
C
fCLK = 100 MSPS, fOUT = 5.04 MHz, TA = 25
°
C
fCLK = 100 MSPS, fOUT = 20.2 MHz, TA = 25
°
C
fCLK = 100 MSPS, fOUT = 40.4 MHz, TA = 25
°
C
fCLK = 50 MSPS, fOUT = 1 MHz, TA= 25
°
C,1 MHz span
fCLK = 50 MSPS, fOUT = 5.02 MHz, 2 MHz span
fCLK = 100 MSPS, fOUT= 5.04 MHz, 4 MHz span
–72
THD
Total harmonic distortion
–72
–64
dBc
–70
–70
79
66
77
Spurious free dynamic range to
Nyquist
75
71
dBc
SFDR
58
69
61
62
Spurious free dynamic range
within a window
82
81
78
dBc
Measured single ended into 50
load at IOUT1.
Single-ended output IOUT1, 50
doubly terminated load.
§Measured with a 50%/50% duty cycle (high/low percentage of the clock). Optimum ac linearity is obtained when limiting the duty cycle to a range
from 45%/55% to 55%/45%.
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