參數(shù)資料
型號: THS4211DRB
廠商: Texas Instruments, Inc.
英文描述: LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER
中文描述: 低失真高速電壓反饋型放大器
文件頁數(shù): 2/41頁
文件大小: 1591K
代理商: THS4211DRB
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
PACKAGE DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
THS4211
THS4215
SLOS400D–SEPTEMBER 2002–REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
UNIT
16.5 V
±
V
S
100 mA
Supply voltage, V
S
Input voltage, V
I
Output current, I
O
Continuous power dissipation
Maximum junction temperature, T
J(2)
Maximum junction temperature, continuous operation, long term reliability T
J(3)
Storage temperature range, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
ESD ratings
CDM
MM
See Dissipation Rating Table
150
°
C
125
°
C
–65
°
C to 150
°
C
300
°
C
4000 V
1500 V
200 V
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
(2)
(3)
POWER RATING
(3)
T
A
25
°
C
1.02 W
1.71 W
385 mW
2.18 W
θ
θ
JA(2)
(
°
C/W)
PACKAGE
(
°
C/W)
T
A
= 85
°
C
410 mW
685 mW
154 mW
873 mW
D (8 pin)
DGN (8 pin)
(1)
DGK (8 pin)
DRB (8 pin)
38.3
4.7
54.2
5
97.5
58.4
260
45.8
(1)
The THS4211/5 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125
°
C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125
°
C for best performance and long
term reliability.
(2)
(3)
MIN
±
2.5
5
V
S–
+ 1.2
MAX
±
7.5
15
V
S+
– 1.2
UNIT
Dual supply
Single supply
Supply voltage, (V
S+
and V
S–
)
V
Input common-mode voltage range
V
2
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