參數資料
| 型號： | THS1230IPWRG4 |
| 廠商： | Texas Instruments |
| 文件頁數： | 5/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 30MSPS 12BIT LP 28-TSSOP |
| 產品培訓模塊： | Data Converter Basics |
| 標準包裝： | 2,000 |
| 位數： | 12 |
| 采樣率（每秒）： | 30M |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 220mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個差分，單極 |
| 配用： | 296-10012-ND - EVALUATION MODULE FOR THS1230 |
www.ti.com
SAMPLE
AND
HOLD
AIN
AIN+
+1
1
VP+
VP
REFT
REFB
ADC
CORE
Sample and Hold
Analog-to-Digital Converter
Analog Input
THS1230
RS
VS+
VS
RS
RSW
CI
VCM
_
+
_
+
R
S t
1
2f
CLK
C
I
In(256)
–R
SW
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
Figure 15. Analog Input Signal Flow
The differential sample and hold processes AIN with respect to the voltages applied to the REFT and REFB pins,
to give a differential output (VP+) – (VP–) = VP given by:
VP = (AIN+) – ( AIN–)
No matter what operating configuration is chosen, VP is digitized against ADC reference voltages VREFT and
VREFB. The VREFT and VREFB voltages set the analog input span limits FS+ and FS–, respectively. Any voltages at
AIN greater than REFT or less than REFB causes ADC over-range, which is signaled by OVR going high when
the conversion result is output.
A first-order approximation for the equivalent analog input circuit of the THS1230 is shown in Figure 16. The
equivalent input capacitance CI is 5 pF typical. The input must charge/discharge this capacitance within the
sample period of one half of a clock cycle. When a full-scale voltage step is applied, the input source provides
the charging current through the switch resistance RSW (200 ) of S1 and quickly settles. In this case the input
impedance is low. Alternatively, when the source voltage equals the value previously stored on CI, the hold
capacitor requires no input current and the equivalent input impedance is very high.
Figure 16. Simplified Equivalent Input Circuit
To maintain the frequency performance outlined in the specifications, the total source impedance should be
limited to the following equation with fCLK = 30 MHz, CI = 5 pF, RSW = 200 :
So, for applications running at a lower fCLK, the total source resistance can increase proportionally.
13
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