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參數(shù)資料
| 型號： | THS1230CPWG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 10/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 30MSPS 12BIT LP 28-TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Basics |
| 標準包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 30M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 220mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
| 配用： | 296-10012-ND - EVALUATION MODULE FOR THS1230 |
www.ti.com
Analog Input Bandwidth
Output Timing
Signal-to-Noise Ratio + Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
THS1230
SLAS291B – OCTOBER 2000 – REVISED MARCH 2004
The analog input bandwidth is defined as the maximum frequency of a 1-dBFS input sine wave that can be
applied to the device for which an extra 3-dB attenuation is observed in the reconstructed output signal.
Output timing td(O) is measured from the 50% level of the CLK input falling edge to the 10%/90% level of the
digital output. The digital output load is not higher than 10 pF.
Output hold time th(O) is measured from the 50% level of the CLK input falling edge to the10%/90% level of the
digital output. The digital output load is not less than 2 pF.
Aperture delay td(A) is measured from the 50% level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing td(PZ) is measured from the VIH(min) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OE timing td(EN) is measured from the VIL(max) level of OE to the instant when the output data reaches VOH(min) or
VOL(max) output levels. The digital output load is not higher than 10 pF.
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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參數(shù)描述 |
|---|---|
| THS1230CPWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low Power High-Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1230CPWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low Power High-Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1230EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 THS1230 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| THS1230IDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low Power High-Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1230IDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low Power High-Speed ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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