參數(shù)資料
型號(hào): THS1031CPWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁(yè)數(shù): 24/41頁(yè)
文件大?。?/td> 728K
代理商: THS1031CPWRG4
THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
details
The above value for RAIN is derived by noting that the average AIN voltage must equal the bias voltage supplied
by the ac coupling network. The average value of VLAST in equation 13 is thus a constant voltage
VLAST = V(AIN bias) – VM
For an input voltage Vin at the AIN pin,
Qin = (VIN – VLAST) × CS
Provided that f (–3 dB) is much lower than fclk, a constant current flowing over the clock period can approximate
the input charging pulse
IIN
= Qin/tclk
= Qin
× fclk
= (Vin – VLAST) × CS × fclk
The ac input resistance RAIN is then
RAIN = dIin/dVin
= 1 / (dVin / dIin)
= 1 / (CS x fclk)
driving the VREF pin (differential mode)
Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin
(MODE = AVDD/2 and REFSENSE = AVDD).
AVDD
AGND
AVDD + VREF/4
VREF
RIN
14 k
REFSENSE = AVDD,
Mode =
_
+
44
AVDD
2
Figure 35. Equivalent Circuit of VREF
The current flowing into IIN is given by
I
IN +
(3
VREF
* AV
DD
)
(4
R
IN
)
Note that the actual IIN may differ from this value by up to 50% due to device-to-device processing variations
and allowing for operating temperature variations.
The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground
and capable of driving IIN.
(13)
(14)
(15)
(16)
(17)
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