參數(shù)資料
型號(hào): THS1031CDWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, SOIC-28
文件頁(yè)數(shù): 22/42頁(yè)
文件大小: 730K
代理商: THS1031CDWRG4
THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
AIN input current and input load modeling (continued)
AIN
R< 20
VS
Figure 33. Damping Source Ringing Using a Small Resistor
equivalent input resistance at AIN and ac-coupling to AIN
Some applications may require ac-coupling of the input signal to the AIN pin. Such applications can use an
ac-coupling network such as shown in Figure 34.
AIN
AVDD
R(Bias1)
R(Bias2)
Cin
Figure 34. AC-Coupling the Input Signal to the AIN Pin
Note that if the bias voltage is derived from the supplies, as shown in Figure 34, then additional filtering should
be used to ensure that noise from the supplies does not reach AIN.
Working with the input current pulse equations given in the previous section is awkward when designing
ac-coupling input networks. For such design, it is much simpler to model the AIN input as an equivalent
resistance, RAIN, from the AIN pin to a voltage source VM where
VM = (REFTS + REFBS)/2 and RAIN = 1 / (CS x fclk)
where fclk is the CLK frequency.
The high-pass –3 dB cutoff frequency for the circuit shown in Figure 34 is:
f
(
*3dB) +
1
2
p
R
IN
tot
where RINtot is the parallel combination of Rbias1, Rbias2, and RAIN. This approximation is good provided that
the clock frequency, fclk, is much higher than f(–3 dB).
Note also that the effect of the equivalent RAIN and VM at the AIN pin must be allowed for when designing the
bias network dc level.
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