參數(shù)資料
型號： THS1009CDAR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： PLASTIC, TSSOP-32
文件頁數(shù)： 7/31頁
文件大?。?/td> 289K
代理商： THS1009CDAR
THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
15
Figure 25 shows the timing of the conversion when one analog input channel is selected. The maximum throughput
rate is 8 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information
is not required for one analog input. There is a certain timing relationship required for the read signal with respect
to the conversion clock. This can be seen in Figure 26 and the timing specification. A more detailed description of
the timing is given in the section timing and signal description of the THS1009.
Sample N
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+1
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7
Channel 1
Sample N+8
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
AIN
CONV_CLK
READ
READ is the logical combination from CS0, CS1 and RD
tw(CONV_CLKH)
td(A)
td(pipe)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
Figure 25. Conversion Timing in 1-Channel Operation
Figure 27 shows the conversion timing when two analog input channels are selected. The maximum throughput rate
per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data
is available to the data bus. This can be seen in Figure 26 and Table 2. A more detailed description of the timing is
given in the section timing and signal description of the THS1009.
Sample N
Channel 1, 2
Sample N+1
Channel 1, 2
Sample N+2
Channel 1, 2
Sample N+3
Channel 1, 2
Sample N+4
Channel 1, 2
td(pipe)
td(A)
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
READ is the logical combination from CS0, CS1 and RD
AIN
CONV_CLK
READ
SYNC
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
tsu(CONV_CLKL-SYNCL)
tsu(CONV_CLKL-SYNCH)
Figure 26. Conversion Timing in 2-Channel Operation
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS1009CDARG4 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
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THS1009IDA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 BIT QUAD ADC w/o RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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THS1009IDAR 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
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