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參數(shù)資料
| 型號(hào)： | THMC41SOPD |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS |
| 中文描述： | 變速12伏直流無(wú)刷風(fēng)扇電機(jī)驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大小： | 238K |
| 代理商： | THMC41SOPD |
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THMC40, THMC41
VARIABLE SPEED 12-VDC BRUSHLESS FAN MOTOR DRIVERS
SLIS097 – MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
dc
electrical characteristics, V
PWR
= 12 V, T
A
= –30
°
C to 80
°
C (unless otherwise noted) (continued)
V
PWM
high-side PWM duty cycle adjust input
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
μ
A
V
IIB(PWM)
VPWM (100%)
VSLEEP
VPWM input bias current
VPWM voltage equivalent to 100% duty cycle
VPWM voltage threshold to engage sleep mode
VPWM voltage threshold to disengage sleep
mode
VPWM = 0 V to 3 V
±
1
2.3
0.6
0.7
V
VSTART
0.8
0.9
V
thermal shutdown characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TTSD
VOUT, PHA, PHB global thermal shutdown
thresholds
Temperature increasing until outputs are off,
See Note 6
150
185
°
C
THYST
Thermal shutdown hysteresis
After TTSD, temperature decreasing until out-
puts return to normal operation, See Note 6
15
°
C
TACH Tachometer open-drain output (THMC40)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
μ
A
V
ITACHLEAK
VOL
TACH high-level output leakage current
VTACH = 5 V
ITACH = 5 mA
0.1
1
TACH low-level output voltage
0.1
0.3
RD locked rotor detection open-drain output (THMC41)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
μ
A
V
IRDLEAK
VOL
RD high-level output leakage current
VRD = 5 V, Locked rotor condition
IRD = 5 mA, No locked rotor
0.1
1
RD low-level output voltage
0.1
0.3
ac electrical characteristics, V
PWR
= 12 V, T
A
= –30
°
C to 80
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
fPWM
tRD
tRETRY
tHALL
tDEAD(PHx)
tf(OUT)
tr(OUT)
tf(PHx)
tr(PHx)
NOTE 6: Design targets only. Not tested in production.
High-side gate drive PWM frequency
COSC = 2200 pF
22.7
kHz
Locked rotor detect delay time
COSC= 2200 pF See Figure 9
COSC = 2200 pF, See Figure 9
1
s
Auto-restart delay time
8
s
Hall zero-crossing deglitch time
See Figure 2
25
μ
s
μ
s
ns
Dead time between phase commutations
5
VOUT output fall time
VOUT output rise time
PHA or PHB fall time
PHA or PHB rise time
25
RL = 20
, LL = 5 mH,
See Note 6
25
ns
μ
s
μ
s
1
1
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