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參數(shù)資料
| 型號： | TFP7401 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 130K |
| 代理商： | TFP7401 |
TFP7401
SXGA+/UXGA TFT LCD PANEL TIMING CONTROLLER
WITH MINILVDS AND FLATLINK
SLDS126 – APRIL 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
serial EEPROM interface
This block controls controller initialization. At power-up, the controller configures the internal programmable
registers with data from the EEPROM.
If there is no acknowledge signal of 7 bit device select code and 1 bit read/xwrite designator (indicating EEPROM
not present), internal ROM values are used to initialize the controller.
fail-safe circuit
The controller detects the off-spec control timing from the host. The controller has a self-oscillator circuit used
for the off-spec timing detection. If the off-spec condition is detected, this circuit generates the default video
stream and control timing to the source drivers and gate drivers. This function prevents biasing dc voltage to
the LCD panel.
pin description
system interface
SYMBOL
PIN COUNT
TYPE
FUNCTION
ERX0P/M
2
LVDS Rx
FlatLink data differential pair 0 input
ERX1P/M
2
LVDS Rx
FlatLink data differential pair 1 input
ERX2P/M
2
LVDS Rx
FlatLink data differential pair 2 input
ERXCLKP/M
2
LVDS Rx
FlatLink clock differential pair input
ORX0P/M
2
LVDS Rx
FlatLink data differential pair 0 input
ORX1P/M
2
LVDS Rx
FlatLink data differential pair 1 input
ORX2P/M
2
LVDS Rx
FlatLink data differential pair 2 input
ORXCLKP/M
2
LVDS Rx
FlatLink clock differential pair input
mini-LVDS source driver interface
SYMBOL
PIN COUNT
TYPE
FUNCTION
LLV0P/M
2
Tx
Left half mini-LVDS data differential pair 0
LLV1P/M
2
Tx
Left half mini-LVDS data differential pair 1
LLV2P/M
2
Tx
Left half mini-LVDS data differential pair 2
LLV3P/M
2
Tx
Left half mini-LVDS data differential pair 3
LLV4P/M
2
Tx
Left half mini-LVDS data differential pair 4
LCLKP/M
2
Tx
Left half mini-LVDS Clock differential pair
RLV0P/M
2
Tx
Right half mini-LVDS data differential pair 0
RLV1P/M
2
Tx
Right half mini-LVDS data differential pair 1
RLV2P/M
2
Tx
Right half mini-LVDS data differential pair 2
RLV3P/M
2
Tx
Right half mini-LVDS data differential pair 3
RLV4P/M
2
Tx
Right half mini-LVDS data differential pair 4
RCLKP/M
2
Tx
Right half mini-LVDS Clock differential pair
TP1
1
Output
Horizontal syncronous output
POL
1
Output
Polarity inversion output
gate driver interface
SYMBOL
PIN COUNT
TYPE
FUNCTION
CPV
1
Output
Sift clock for gate driver
STVA, STVB
2
Output
Start pulse output to gate driver
OE
1
Output
Gate driver output enable
PRODUCT
PREVIEW
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