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參數(shù)資料
| 型號： | TFP513PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.00 MM HEIGHT, 0.50 MM PITCH, HTQFP-64 |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 1206K |
| 代理商： | TFP513PAP |
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TFP513
TI PanelBus DIGITAL TRANSMITTER
SLLS611 AUGUST 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f(IDCK)
IDCK frequency
25
165
MHz
t(pixel)
Pixel time period (see Note 4)
6.06
40
ns
t(IDCK)
IDCK duty cycle
30%
70%
t(ijit)
IDCK clock jitter tolerance
2
ns
tr
DVI output rise time (2080%) (see Note 5)
75
240
tf
DVI output fall time (2080%) (see Note 5)
75
240
ps
tsk(D)
DVI output intra-pair + to differential skew (see Note 6)
f(IDCK) = 165 MHz
50
ps
tsk(CC)
DVI output inter-pair or channel-to-channel skew (see Note 6)
f(IDCK) = 165 MHz
1.2
ns
tojit
Output clock jitter, maximum (see Note 7)
150
ps
tsu(IDF)
Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge
Single edge
(BSEL = 1, DSEL = 0,
1.2
ns
th(IDF)
Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge
(BSEL = 1, DSEL = 0,
DKEN = 0, EDGE = 0)
1.3
ns
tsu(IDR) Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge
Single edge
(BSEL = 1, DSEL = 0,
1.2
ns
th(IDR)
Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge
(BSEL = 1, DSEL = 0,
DKEN = 0, EDGE = 1)
1.3
ns
tsu(ID)
Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising edge
Dual edge
(BSEL = 0, DSEL = 1,
0.9
ns
th(ID)
Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising edge
(BSEL = 0, DSEL = 1,
DKEN = 0)
1
ns
t(STEP)
De-skew trim increment
DKEN = 1
350
ps
NOTES:
4. t(pixel) is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t(pixel).
5. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.
6. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.
7. Relative to input clock (IDCK).
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