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參數(shù)資料
| 型號： | TFP401AMPZPEP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 460K |
| 代理商： | TFP401AMPZPEP |
FUNCTIONAL BLOCK DIAGRAM
_
+
Latch
Channel 2
_
+
Latch
Channel 1
_
+
Latch
Channel 0
_
+
PLL
Data Recovery
and
Synchronization
TMDS
Decoder
CH2(0-9)
CH1(0-9)
CH0(0-9)
Panel
Interface
RED(0-7)
CTL3
CTL2
GRN(0-7)
CTL1
BLU(0-7)
VSYNC
HSYNC
QE(0-23)
QO(0-23)
ODCK
DE
SCDT
CTL3
CTL2
CTL1
VSYNC
HSYNC
1.8 V
Regulator
3.3 V
Internal 50-
Termination
3.3 V
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
www.ti.com .................................................................................................................................................................................................. SLDS160 – MARCH 2009
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
79, 83, 87, 89, 92
GND
Analog Ground - Ground reference and current return for analog circuitry.
AVDD
82, 84, 88, 95
VDD
Analog VDD - Power supply for analog circuitry. Nominally 3.3 V
General-purpose control signals - Used for user defined control. CTL1 is not powered-down
CTL[3:1]
42, 41, 40
DO
via PDO.
Output data enable - Used to indicate time of active video display versus non-active display
or blank time. During blank, only HSYNC, VSYNC, and CTL1-3 are transmitted. During times
DE
46
DO
of active display, or non-blank, only pixel data, QE[23:0] and QO[23:0], is transmitted.
High : Active display time
Low: Blank time
Output clock data format - Controls the output clock (ODCK) format for either TFT or DSTN
panel support. For TFT support ODCK clock runs continuously. For DSTN support ODCK
DFO
1
DI
only clocks when DE is high, otherwise ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
DGND
5, 39, 68
GND
Digital ground - Ground reference and current return for digital core
DVDD
6, 38, 67
VDD
Digital VDD - Power supply for digital core. Nominally 3.3 V
Internal impedance matching - The TFP401A is internally optimized for impedance matching
EXT_RES
96
AI
at 50 W. An external resistor tied to this pin has no effect on device performance.
HSYNC
48
DO
Horizontal sync output
RSVD
99
DI
Reserved. Must be tied high for normal operation.
OVDD
18, 29, 43, 57, 78
VDD
Output driver VDD - Power supply for output drivers. Nominally 3.3 V
Output data clock - Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock
ODCK
44
DO
mode) along with DE, HSYNC, VSYNC and CTL[3:1] are synchronized to this clock.
OGND
19, 28 ,45, 58, 76
GND
Output driver ground - Ground reference and current return for digital output drivers
ODCK Polarity - Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and
control signals (HSYNC, VSYNC, DE, CTL1-3 ) are latched.
OCK_INV
100
DI
Normal Mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
Copyright 2009, Texas Instruments Incorporated
3
Product Folder Link(s): TFP401A-EP
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| TFP401APZP | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr 165MHz HSYNC fix RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP401APZPG4 | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
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| TFP403 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TI PANEBUS DIGITAL RECEIVER |
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