參數(shù)資料
型號: TFP401ACPZP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁數(shù): 7/22頁
文件大小: 285K
代理商: TFP401ACPZP
TFP401, TFP401A
TI PanelBus
DIGITAL RECEIVER
SLDS120 - MARCH 2000
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TFP401/401A modes of operation
The TFP401/401A provides systems design flexibility and value by providing the system designer with
configurable options or modes of operation to support varying system architectures. The following table outlines
the various panel modes that can be supported along with appropriate external control pin settings.
PANEL
PIXEL RATE
ODCK LATCH
EDGE
ODCK
DFO
PIXS
OCK_INV
TFT or 16-bit DSTN
1 pix/clock
Falling
Free run
0
TFT or 16-bit DSTN
1 pix/clock
Rising
Free run
0
1
TFT
2 pix/clock
Falling
Free run
0
1
0
TFT
2 pix/clock
Rising
Free run
0
1
24-bit DSTN
1 pix/clock
Falling
Gated low
1
0
NONE
1 pix/clock
Rising
Gated low
1
0
1
24-bit DSTN
2 pix/clock
Falling
Gated low
1
0
24-bit DSTN
2 pix/clock
Rising
Gated low
1
TFP401/401A output driver configurations
The TFP401/401A provides flexibility by offering various output driver features that can be used to optimize
power consumption, ground-bounce and power-supply noise. The following sections outline the output driver
features and their effects.
Output driver power down (PDO = low), Pulling PDO low will place all the output drivers, except CTL1 and
SCDT, into a high-impedance state. A weak pulldown (approximately 10
A) will gradually pull these Hi-Z
outputs to a low level to prevent the outputs from floating. The SCDT output which indicates link-disabled or
link-inactive can be tied directly to the PDO input to disable the output drivers when the link is inactive or when
the cable is disconnected. An internal pullup on the PDO pin will default the TFP401/401A to the normal
nonpower down output drive mode if left unconnected.
Drive Strength (ST = high for high drive strength, ST=low for low drive strength.) The TFP401/401A allows
for selectable output drive strength on the data, control and ODCK outputs. See the dc specifications table for
the values of IOH and IOL current drives for a given ST state. The high output strength offers approximately two
times the drive as the low output drive strength.
Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high).
Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous
current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount
of system ground bounce and power supply noise. The time stagger is such that in 2-pixel/clock mode the even
pixel is delayed from the latching edge of ODCK by 0.25 Tcip. (Tcip is the period of ODCK. The ODCK period
is 2Tpix when in 2-pixel/clock mode.)
Depending on system constraints of output load, pixel rate, panel input architecture and board cost the
TFP401/401A drive strength and staggered pixel options allow flexibility to reduce system power-supply noise,
ground bounce and EMI.
Power Management. The TFP401/401A offers several system power management features. The following
table outlines the basic TFP401/401A power modes.
ADV
ANCE
INFORMA
TION
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