參數(shù)資料
型號(hào): TEA5777HN/N2,518
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: AM/FM, AUDIO SINGLE CHIP RECEIVER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-1, HVQFN-48
文件頁數(shù): 8/47頁
文件大?。?/td> 219K
代理商: TEA5777HN/N2,518
TEA5777_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 11 April 2006
16 of 47
Philips Semiconductors
TEA5777
Low-power AM/FM stereo radio for handheld applications
9.3 I2C-bus mode
The I2C-bus interface is based on
‘The I2C-bus specication’ version 2.1 January 2000.
In the I2C-bus mode, only pins CLOCK and DATA are used for data transfer. The level on
pin WRITE_READ is don’t care.
Data transfer to the bus interface is byte oriented and no sub-addressing is used.
The data transfer consists of a START condition, device address byte plus R/W
Data is written at the rising edge and data is clocked out at the falling edge. The I2C-bus
can operate at a maximum clock frequency of 400 kHz.
The I2C-bus device address of the TEA5777 is: 110 0000 (7 bits).
9.3.1 Write mode
The bus interface has a total of 6 write registers. Before data can be written to these
registers, the I2C-bus device address byte has to be written to the IC
After the bus interface (slave) recognizes a start of transmission, the address byte is
written to the bus. If the address is equal to the internal address of the bus interface, an
acknowledge is given to the master and data can be written to the write registers.
If the bus address does not match, no acknowledge is given and the internal bus interface
clock is disabled until a next start is detected.
Table 4.
I2C-bus data transfer
Condition
Byte
Description
START
start by master
Address byte
device address + R/W bit
ACK
acknowledge by slave
Byte 1
data byte 1
ACK
acknowledge by slave
Byte 2
data byte 2
ACK
acknowledge by slave
Byte n
data byte n
ACK
acknowledge by slave
STOP
stop by master
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