
SMART 3 ADVANCED BOOT BLOCK
E
20
PRELIMINARY
3.3
Block Locking
The Smart 3 Advanced Boot Block flash memory
architecture
features
parameter blocks.
two
hardware-lockable
3.3.1
WP# = V
IL
FOR BLOCK LOCKING
The lockable blocks are locked when WP# = V
IL
;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
parameter blocks (blocks #69 and #70, blocks #37
and #38 for the 16-Mbit, blocks #21 and #22 for the
8-Mbit, blocks #13 and #14 for the 4-Mbit) are
lockable. For the bottom configuration, the bottom
two parameter blocks (blocks #0 and #1 for 4-/8-/
16-/32-Mbit) are lockable. Unlocked blocks can be
programmed or erased normally (unless V
PP
is
below V
PPLK
).
3.3.2
WP# = V
IH
FOR BLOCK UNLOCKING
WP# = V
IH
unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in
previous Boot Block devices. WP# controls all block
locking and V
PP
provides protection against
spurious writes. Table 8 defines the write protection
methods.
Table 8. Write Protection Truth Table for
Advanced Boot Block Flash Memory Family
V
PP
WP#
RP#
Write Protection
Provided
X
X
V
IL
All Blocks Locked
V
IL
X
V
IH
All Blocks Locked
≥
V
PPLK
V
IL
V
IH
Lockable Blocks
Locked
≥
V
PPLK
V
IH
V
IH
All Blocks Unlocked
3.4
V
PP
Program and Erase
Voltages
Intel’s Smart 3 products provide in-system
programming and erase at 2.7 V. For customers
requiring fast programming in their manufacturing
environment, Smart 3 includes an additional low-
cost 12 V programming feature.
The 12 V V
PP
mode enhances programming
performance during the short period of time typically
found in manufacturing processes; however, it is
not intended for extended use. 12 V may be applied
to V
PP
during program and erase operations for a
maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. V
PP
may be
connected to 12 V for a total of 80 hours maximum.
Stressing the device beyond these limits may cause
permanent damage.
During read operations or idle times, V
PP
may be
tied to a 5 V supply. For program and erase
operations, a 5 V supply is not permitted. The V
PP
must be supplied with either 2.7 V–3.6 V or 11.4 V–
12.6 V during program and erase operations.
3.4.1
V
= V
FOR COMPLETE
PROTECTION
The V
PP
programming voltage can be held low for
complete write protection of all blocks in the flash
device. When V
PP
is below V
PPLK
, any program or
erase operation will result in a error, prompting the
corresponding status register bit (SR.3) to be set.
3.5
Power Consumption
Intel Flash devices have a tiered approach to
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is selected but idle. If the CE# is
deasserted, the flash enters its standby mode,
where current consumption is even lower. The
combination of these features can minimize
memory power consumption, and therefore, overall
system power consumption.