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參數(shù)資料
| 型號(hào)： | TE28F010-120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 120 ns, PDSO32 |
| 封裝： | 0.310 X 0.720 INCH, TSOP-32 |
| 文件頁(yè)數(shù)： | 8/33頁(yè) |
| 文件大?。?/td> | 895K |
| 代理商： | TE28F010-120 |
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28F010
E
8
290207-4
Figure 3. 28F010 in a 80C186 System
2.0
PRINCIPLES OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power
supplies during erasure and programming; and
maximum EPROM compatibility.
In the absence of high voltage on the V
PP
pin, the
28F010 is a read-only memory. Manipulation of the
external memory control pins yields the standard
EPROM read, standby, output disable, and
intelligent identifier operations.
The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the V
PP
pin. In addition, high voltage
on V
PP
enables erasure and programming of the
device. All functions associated with altering
memory
contents
—intelligent
erase verify, program, and program verify—are
accessed via the command register.
identifier,
erase,
Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and
data needed for programming or erase operations.
With the appropriate command written to the
register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output data for erase and program
verification.
2.1
Integrated Stop Timer
Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations are
normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminating the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminates a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TE28F010-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| TE28F010-90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| TE28F016 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016B3B110 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| TE28F016B3B120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE |
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