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參數(shù)資料
| 型號(hào)： | TDA8798 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual 8-bit, 100 Msps A/D converter with DPGA |
| 中文描述： | 雙8位，100 Msps的的A / D轉(zhuǎn)換器與DPGA |
| 文件頁(yè)數(shù)： | 12/24頁(yè) |
| 文件大?。?/td> | 214K |
| 代理商： | TDA8798 |
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1999 Sep 16
12
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
N
OISE
V
n(o)(rms)
output referred noise
(RMS value)
DPGA at G
(max)
;
Z
i
= 50
; noise
bandwidth = 15 MHz
tbf
2
mV
rms
ADC (without DPGA; f
CLK
= 100 MHz; from buffer input to digital output)
A
NALOG INPUTS
(BUF1, BUF1N, BUF2
AND
BUF2N)
V
i(dif)(FS)(p-p)
differential input voltage
full-scale amplitude;
(peak-to-peak value)
common mode input voltage
input current
input resistance
input capacitance
500
mV
V
i(cm)(ADC)
I
i(ADC)
R
i(ADC)
C
i(ADC)
S
TATIC LINEARITY
tbf
tbf
20
3
V
μ
A
k
pF
at V
i(cm)(ADC)
NL
dc(i)
DC integral non-linearity
ramp input;
without DPGA
with DPGA
at G
(min)
ramp input;
without DPGA
with DPGA
at G
(min)
±
1.0
±
3.0
tbf
tbf
LSB
LSB
NL
dc(dif)
DC differential non-linearity
±
0.5
±
0.5
tbf
tbf
LSB
LSB
D
YNAMIC PERFORMANCE
THD
S/N
total harmonic distortion
signal-to-noise ratio
f
i
= 4.43 MHz
without harmonics
55
46
dB
dB
B
ANDWIDTH
B
(
3dB)(ADC)
C
ROSSTALK BETWEEN
ADC1
AND
ADC2
α
ct
crosstalk between channels
C
LOCK INPUTS
: CLK1, CLK1N, CLK2
AND
CLK2N; note 1
ADC
3 dB analog bandwidth
120
MHz
40
dB
V
IL
V
IH
I
IH
I
IL
D
IGITAL CONTROL INPUTS
(OE, TE, TEST, DPGAEN
AND
SR)
LOW-level clock input voltage
HIGH-level clock input voltage
HIGH-level clock input current
LOW-level clock input current
2.0
100
0.8
V
DDD
100
V
V
μ
A
μ
A
V
IL
V
IH
I
IH
I
IL
LOW-level input voltage
HIGH-level input voltage
HIGH-level input current
LOW-level input current
2.0
5
5
0.8
V
DDD
+5
+5
V
V
μ
A
μ
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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