參數(shù)資料
型號： TDA8769HW/6
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝： 7 X 7 MM, 1.0 MM HEIGHT, PLASTIC, HTQFP-48
文件頁數(shù)： 28/28頁
文件大?。?/td> 232K
代理商： TDA8769HW/6
2003 Dec 09
9
Philips Semiconductors
Objective specication
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling
TDA8769
Reference voltage input: pin VREF; note 3
Vref(FS)
full-scale xed
voltage
fi = 25 MHz;
fCLK = 105 Msps
VCCA3 1.75
V
Vi(p-p)
input voltage
(peak-to-peak
value)
Vi =VIN VINN;
VVREF =VCCA3 1.75 V;
Vi(CM) =VCCA3 1.6 V
1.9
V
Iref
input current
0.3
10
A
Full-scale voltage controlled regulator output: pin FSREF
Vo(FS)
1.9 V full-scale
output voltage
VCCA3 1.75
V
IL(FS)
load current
12
mA
Digital outputs: pins D11 to D0 and IR
OUTPUT LEVELS
VOL
LOW-level
output voltage
IOL = 2 mA
DGND
DGND + 0.5 V
VOH
HIGH-level
output voltage
IOH = 0.4 mA
VCCO 0.5
VCCO
V
IOZ
output current in
3-state
output level between
0.5 V and VCCO
20
+20
A
TIMING; see Fig. 3
td(s)
sampling delay
CL = 10 pF; note 4
(tbf)
ns
th(o)
output hold time
CL = 10 pF
(tbf)
3.7
ns
td(o)
output delay
CL =10pF
4.6
(tbf)
ns
3-STATE OUTPUT DELAY
tdZH
enable to HIGH
state
2.8
ns
tdZL
enable to LOW
state
7.5
ns
tdHZ
disable from
HIGH state
7.2
ns
tdLZ
disable from
LOW state
2.9
ns
Timing complete conversion signal: pin CCS
td(CCS)
complete
conversion
signal delay
CL = 10 pF; see Table 4
and Fig 4
DEL0 = LOW;
DEL1 = HIGH
0
ns
DEL0 = HIGH;
DEL1 = LOW
1.2
ns
DEL0 = HIGH;
DEL1 = HIGH
2.2
ns
SYMBOL
PARAMETER
CONDITIONS
TEST(1)
MIN.
TYP.
MAX.
UNIT
相關(guān)PDF資料
PDF描述
TDA8769HW/8 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
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