參數(shù)資料
型號: TDA8767H/2-T
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 20/20頁
文件大?。?/td> 103K
代理商: TDA8767H/2-T
1999 Feb 16
9
Philips Semiconductors
Preliminary specication
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
Notes to the characteristics
1. The
3 dB (or 1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data (see Fig.5).
4. Output data acquisition: the output data is available after the maximum delay of td.
SIGNAL-TO-NOISE RATIO
S/N
signal-to-noise ratio
without harmonics;
fclk = 30 MHz; fi = 4.43 MHz
61
dB
Timing (CL = 15 pF); note 4; see Fig.3
tds
sampling delay time
2ns
th
output hold time
8
ns
td
output delay time
VCCO = 4.75 V
12
15
ns
VCCO = 3.15 V
15
18
ns
3-state output delay times; see Fig.4
tdZH
enable HIGH
14
18
ns
tdZL
enable LOW
16
20
ns
tdHZ
disable HIGH
16
20
ns
tdLZ
disable LOW
14
18
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
THD
20 log
F
(2nd)
2
(3rd)
2
(4th)
2
(5th)
2
(6th)
2
++
+
---------------------------------------------------------------------------------------------------------------
=
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